Semiconductor device including in wafer inductors, related method and design structure
An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first set of trenches formed in a first surface of the substrate; a second set of trenches formed in a second surface of the substrate; and at least one through silicon via connecting the first set of trenches and the second set of trenches.
1. A semiconductor device comprising:
a substrate;
a first set of trenches formed in a first surface of the substrate, a first trench of the first set of trenches extending to a first depth within the substrate;
a second set of trenches formed in a second surface of the substrate opposite the first surface, a second trench of the second set of trenches disposed laterally adjacent the first trench and extending to a second depth within the substrate, the second depth extending beyond the first depth; and
a third trench of the first set of trenches extending to a third depth within the substrate to meet a fourth trench of the second set of trenches extending to a fourth depth within the substrate, thereby forming a through silicon via connecting the first set of trenches and the second set of trenches.
2. The semiconductor device of claim 1 , wherein the first set of trenches are filled with a material forming a first inductor and the second set of trenches are filled with the material forming a second inductor.
3. The semiconductor device of claim 2 , wherein the first inductor and the second inductor are connected via the through silicon via to form a transformer.
4. The semiconductor device of claim 1 , wherein the first set of trenches and the second set of trenches are interleaved in the substrate.
5. The semiconductor device of claim 2 , further comprising a back end of line (BEOL) inductor connected to at least one of the first inductor and the second inductor.
6. The semiconductor device of claim 1 , wherein the first set of trenches and the second set of trenches are connected by a plurality of through silicon vias to form a lateral inductor.
7. The semiconductor device of claim 6 , further comprising a back end of line (BEOL) inductor connected to the lateral inductor to form a transformer.
8. A method, comprising:
forming a first set of trenches in a first surface a substrate, a first trench of the first set of trenches extending to a first depth within the substrate;
performing back end of line (BEOL) processing;
forming a second set of trenches in a second surface the substrate opposite the first surface, a second trench of the second set of trenches disposed laterally adjacent the first trench and extending to a second depth within the substrate, the second depth extending beyond the first depth;
extending at least one trench of the second set of trenches to meet at least one trench of the second set of trenches, thereby forming a through silicon via connecting the first set of trenches and the second set of trenches.
9. The method of claim 8 , wherein a depth of the through silicon via is controlled by regulating a width of the through silicon via.
10. The method of claim 8 , further comprising reducing a thickness of the substrate.
11. The method of claim 8 , further comprising:
connecting a BEOL inductor to the substrate, the BEOL inductor connected to the first set of trenches and the second set of trenches to form a transformer.
12. A design structure tangibly embodied in a machine readable medium for design, manufacturing, or testing a semiconductor device, the design structure comprising:
a substrate;
a first set of trenches formed in a first surface of the substrate, a first trench of the first set of trenches extending to a first depth within the substrate;
a second set of trenches formed in a second surface of the substrate opposite the first surface, a second trench of the second set of trenches disposed laterally adjacent the first trench and extending to a second depth within the substrate, the second depth extending beyond the first depth; and
a third trench of the first set of trenches extending to a third depth within the substrate to meet a fourth trench of the second set of trenches extending to a fourth depth within the substrate, thereby forming a through silicon via connecting the first set of trenches and the second set of trenches.
13. The design structure of claim 12 , wherein the first set of trenches forms a first inductor and the second set of trenches forms a second inductor.
14. The semiconductor device of claim 13 , wherein the first inductor and the second inductor are connected via the through silicon via to form a transformer.
15. The design structure of claim 14 , wherein the first surface of the substrate and the second surface of the substrate are oriented parallel one another.
16. The design structure of claim 15 , wherein the first set of trenches and the second set of trenches are interleaved in the substrate.
17. The design structure of claim 13 , further comprising a back end of line (BEOL) inductor connected to at least one of the first inductor and the second inductor.
18. The design structure of claim 12 , wherein the first set of trenches and the second set of trenches are connected by a plurality of through silicon vias to form a lateral inductor.
19. The design structure of claim 17 , further comprising a back end of line (BEOL) inductor connected to the lateral inductor to form a transformer.