Semiconductor device with vias on a bridge connecting two buses
View Patent ↗A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses.
1. A semiconductor device, comprising:
a first conductive bus;
a second conductive bus; and
a conductive bridge, wherein the conductive bridge:
is coupled between the first and second conductive buses; and
has a width that is less than a width of the first conductive bus and a width of the second conductive bus; and
three conductive vias in the conductive bridge,
wherein a first distance along the conductive bridge between a first edge of a middle via of the three conductive vias and the first bus is less than a first vacancy migration critical length, and a second distance along the conductive bridge between a second edge of the middle via and the second bus is less than a second vacancy migration critical length.
2. The semiconductor device of claim 1 , wherein:
the first conductive bus has a first length;
the second conductive bus has a second length; and
at least one of the first and second lengths is greater than a predetermined length.
3. The semiconductor device of claim 1 , characterized by the one of a group consisting of:
a volume of the respective one of the first conductive buses is greater than a respective first threshold volume which will cause stress migration in at least one of the three conductive vias; and
a volume of the respective one of the second conductive buses is greater than a respective second threshold volume which will cause stress migration in at least one of the three conductive vias.
4. The semiconductor device of claim 1 characterized by one of a group consisting of:
an area of the first conductive bus is greater than a first threshold area which will cause stress migration in at least one of the three conductive vias; and
an area of the second conductive bus is greater than a second threshold area which will cause stress migration in at least one of the three conductive vias.
5. The semiconductor device of claim 1 , characterized by one of a group consisting of:
the first critical length is determined based on at least one of the width and a length of the first conductive bus; and
the second critical length is determined based on at least one of the width and a length of the second conductive bus.
6. The semiconductor device of claim 1 , wherein:
the first conductive bus is in a first layer of the integrated circuit; and
the second conductive bus is in a second layer of the integrated circuit.
7. The semiconductor device of claim 1 , wherein:
the first and second conductive buses are in a same layer of the integrated circuit.
8. A semiconductor device comprising:
first and second conductive buses;
a conductive bridge, wherein a respective conductive bridge is conductively coupled the first and second conductive buses; and
three vias in the conductive bridge when:
a width of the conductive bridge is less than a width of each of the the first and second conductive buses to which the conductive bridge is coupled, and
a distance along the conductive bridge from the first conductive bus to a middle of the three vias is less than a first vacancy migration critical distance and a distance along the conductive bridge from the second conductive bus to the middle of the three vias is less than a second migration critical distance.
9. The semiconductor device of claim 8 , wherein:
the first conductive bus is in a first layer of the integrated circuit; and
the second conductive bus is in a second layer of the integrated circuit.
10. The semiconductor device of claim 9 , wherein:
the first and second conductive buses are in a same layer of the integrated circuit.
11. The semiconductor device of claim 8 , wherein
the first respective critical length is determined based on at least one of the width and a length of the first conductive bus, and
the second respective critical length is determined based on at least one of the width and a length of the second conductive bus.
12. The semiconductor device of claim 8 , Characterized by one of the group consisting of:
an area of the first conductive bus is greater than a first threshold area which will cause stress migration in at least one of the three vias; and
an area of the second conductive bus is greater than a second threshold area which will cause stress migration in at least one of the three vias.