Delay locked loop

1. A delay locked loop comprising:

a delay adjusting unit configured to delay a first clock signal in outputting a second clock signal phase-locked with the first clock signal and generate a delay control signal in response to the first clock signal and the second clock signal; and

a variable delay line configured to output a third clock signal by delaying the first clock signal in response to the delay control signal,

wherein the delay adjusting unit includes:

a replica delay unit configured to delay the first clock signal regardless of the delay control signal;

a second variable delay line configured to output the second clock signal by delaying an output of the replica delay unit in response to the delay control signal, wherein the replica delay unit provides the output thereof without receiving an input through the second variable delay line; and

a delay control unit configured to generate the delay control signal in response to the first clock signal and the second clock signal.

2. The delay locked loop of claim 1 , wherein the delay adjusting unit further comprises:

a dividing unit configured to divide the first clock signal and output the divided clock signal to the delay unit.

3. The delay locked loop of claim 1 , wherein the delay caused by the delay adjusting unit is equal to a sum of a delay for performing a locking operation of the delay locked loop and a delay through a clock path.

4. The delay locked loop of claim 1 , further comprising:

an input buffer unit configured to buffer an external clock signal in outputting the first clock signal; and

an output driver configured to output the third clock signal.

5. The delay locked loop of claim 4 , wherein the delay caused by the delay adjusting unit includes a delay through the input buffer unit and a delay through the output driver.

6. The delay locked loop of claim 1 , wherein a loop is formed by the second variable delay line and the delay control unit except for the replica delay unit.

7. The delay locked loop of claim 1 , wherein the variable delay line is configured to delay the first clock signal by a delay equal to a delay through the second variable delay line in response to the delay control signal.

8. A delay locked loop comprising:

a replica delay unit configured to output a first delayed clock by delaying a source clock by a first delay substantially equal to a delay through a clock path;

a delay control unit configured to generate a delay control signal in response to the source clock and the second delayed clock;

a first variable delay line configured to output a delay locked clock by delaying the source clock by a second delay for performing a locking operation of the delay locked loop in response to the delay control signal; and

a second variable delay line configured to output the second delayed clock by delaying the first delayed clock by the second delay in response to the delay control signal,

wherein the replica delay unit delays the source clock regardless of the delay control signal, and the replica delay unit provides its output without receiving an input through the second variable delay line.

9. The delay locked loop of claim 8 , wherein the delay control unit comprises:

a phase comparing unit configured to compare a phase of the source clock with a phase of the second delayed clock; and

a delay control signal generating unit configured to generate the delay control signal in response to a comparison result outputted from the phase comparing unit.

10. The delay locked loop of claim 8 , further comprising:

an input buffer unit configured to buffer an external clock signal in outputting the source clock; and

an output driver configured to output the delay locked clock.

11. The delay locked loop of claim 10 , wherein the first delay is equal to a sum of a delay through the input buffer unit and a delay through the output driver.

12. A delay locked loop comprising:

a dividing unit configured to divide a source clock in outputting a divided clock;

a replica delay unit configured to output a first delayed clock by delaying the divided clock by a first delay;

a delay control unit configured to generate a delay control signal in response to the source clock and a second delayed clock;

a first variable delay line configured to output a delay locked clock by delaying the source clock by a second delay for performing a locking operation of the delay locked loop in response to the delay control signal; and

a second variable delay line configured to output the second delayed clock by delaying the first delayed clock by the second delay in response to the delay control signal,

wherein the replica delay unit delays the source clock regardless of the delay control signal, and the replica delay unit provides its output without receiving an input through the second variable delay line.

13. The delay locked loop of claim 12 , wherein the delay control unit comprises:

a phase comparing unit configured to compare a phase of the source clock with a phase of the second delayed clock; and

a delay control signal generating unit configured to generate the delay control signal in response to a comparison result outputted from the phase comparing unit.

14. The delay locked loop of claim 12 , wherein the first delay is equal to a value generated by subtracting a delay of the dividing unit from a delay through a clock path.

15. The delay locked loop of claim 14 , further comprising:

an input buffer unit configured to buffer an external clock signal to output the source clock; and

an output driver configured to output the delay locked clock.

16. The delay locked loop of claim 15 , wherein the delay equal to a delay through the clock path is equal to a sum of a delay through the input buffer unit and a delay through the output driver.