Failsafe image sensor with real time integrity checking of pixel analog paths and digital data paths

1. A method for testing an image sensor comprising the steps of:

first sampling a first voltage from a pixel in a row, dependent on exposure to light;

performing a first analog-to-digital (A/D) conversion of the first sampled voltage to provide first digital data;

injecting a test signal into the pixel in the row;

second sampling a second voltage from the pixel in the row, after injection of the test signal;

performing a second A/D conversion of the second sampled voltage to provide second digital data; and

transferring the first and second digital data to a processor for assessing validity of the first digital data, based on the second digital data.

2. The method of claim 1 wherein

first sampling the first voltage includes sampling a first reset reference level of the pixel and, subsequently, sampling a first image signal level of the pixel in response to the exposure to the light; and

second sampling the second voltage includes sampling a second image signal level of the pixel in response to the injecting of the test signal and, subsequently, sampling a second reset reference level of the pixel in the row.

3. The method of claim 2 wherein

performing the first A/D conversion of the first sampled voltage includes converting the first reset reference level of the pixel and, subsequently, converting the first image signal level of the pixel; and

performing the second A/D conversion of the second sampled voltage includes converting the second image signal level of the pixel and, subsequently, converting the second reset reference level of the pixel.

4. The method of claim 1 including the step of:

resetting the pixel in the row during a shutter interval, after performing the first A/D conversion; and

performing the second A/D conversion includes performing the second A/D conversion during the shutter interval.

5. The method of claim 1 wherein

injecting the test signal includes injecting a voltage level between VAAPIX and the drain node of a reset transistor disposed in a four-transistor circuit of the pixel.

6. The method of claim 5 wherein

the voltage level injected is a full-scale voltage level of the image sensor.

7. The method of claim 5 wherein

the voltage level injected is a selected voltage level per row provided by a digital-to-analog converter (DAC), and

the selected voltage level varies between zero and a full-scale voltage level of the image sensor, and

the selected voltage level is referred to VAAPIX.

8. The method of claim 1 including the step of:

providing a pedestal voltage to the pixel in the row for reducing clipping of an image, wherein the pedestal voltage is based on a full-scale voltage range of the image sensor; and

injecting the test signal includes injecting a voltage level between VAAPIX and the drain node of a reset transistor disposed in a four-transistor circuit of the pixel, wherein the injected voltage level includes a reversed polarity of the pedestal voltage.

9. The method of claim 1 including the steps of:

after validating the first digital data, transferring the first digital data to an off-chip processor; and

after invalidating the first digital data, preventing transfer of the first digital data to the off-chip processor.

10. A method of testing analog and digital paths of a pixel in a row of an imager, comprising the steps of:

injecting first and second charges into the analog path of the pixel, wherein the first charge is in response to a light exposure and the second charge is in response to a built-in test;

sampling the first and second charges to form an image signal level and a test signal level, respectively;

converting, by an analog-to-digital converter (ADC), the image signal level and the test signal level to form image data and test data, respectively; and

validating the image data based on the test data.

11. The method of claim 10 including the steps of:

first resetting the pixel, prior to injecting the first charge in response to the light exposure, and

second resetting the pixel, after injecting the second charge in response to the built-in test.

12. The method of claim 11 wherein

first resetting the pixel, injecting the first charge, injecting the second charge and second resetting the pixel occur, respectively, at times t 0 , t 1 , t 2 , and t 3 , and

each of the times are in numerical time sequence.

13. The method of claim 11 wherein

the second resetting of the pixel occurs during a shutter period for readying the pixel for the next frame of operation.

14. The method of claim 10 wherein

injecting the second charge includes providing a voltage between VAAPIX and a drain node of a reset transistor disposed in a four-transistor circuit of the pixel.

15. The method of claim 14 wherein

the voltage provided between VAAPIX and the drain node of the reset transistor is supplied by a digital-to-analog converter (DAC), and

the voltage varies between zero and a full-scale voltage level of the image sensor.

16. An image sensor comprising:

a pixel circuit including a reset transistor having a drain node connected to a switchable voltage reference level,

a correlated double sampling (CDS) circuit coupled to the pixel circuit for providing a reset reference level (SHR) and an image signal level (SHS), in response to charges in the pixel circuit, and

a test circuit for providing the switchable voltage reference level,

wherein when the test circuit provides a VAAPIX voltage level to the reset transistor, the CDS circuit provides a first SHR and a first SHS, in response to charges in the pixel circuit due to light exposure, and

when the test circuit provides a predetermined voltage level to the reset transistor, the CDS circuit provides a second SHS, in response to charges in the pixel circuit due to the predetermined voltage level.

17. The image sensor of claim 16 wherein

the CDS circuit is configured to provide a second SHR, in response to charges in the pixel circuit due to the predetermined voltage level, and

the second SHR is provided during a shutter interval for resetting the pixel circuit for the next frame of operation.

18. The image sensor of claim 16 wherein

the test circuit includes a digital-to-analog converter (DAC), and

the DAC is configured to provide the predetermined voltage level, which varies between zero and a full-scale voltage level of the image sensor, and

the predetermined voltage level is referred to VAAPIX.

19. The image sensor of claim 18 wherein

the full-scale voltage level of the image sensor is provided by a pedestal voltage to the pixel circuit for reducing clipping of an image.

20. The image sensor of claim 16 further including:

an on-chip processor coupled to the CDS circuit for receiving digital data, based on the first SHR, first SHS, and second SHS, and transferring validated digital data to an off-chip processor.