Built-in self trim for non-volatile memory reference current
View Patent ↗A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value.
1. A system comprising:
a non-volatile memory (NVM) array;
a NVM reference current generator configured to generate a NVM reference current used to access the NVM array;
an analog-to-digital converter (ADC), coupled to the NVM reference current generator, and configured to convert the NVM reference current to a digital NVM reference current value;
a comparator, coupled to the ADC, and configured to compare the digital NVM reference current value to a target value; and
trim logic, coupled to the comparator, and configured to
provide a control signal for the NVM reference current generator to produce an adjusted NVM reference current if the digital NVM reference current value is outside a range of the target value, wherein
a digital adjusted NVM reference current value is within the range of the target value, and
the range of the target value comprises a lower limit of the range of the target value and an upper limit of the range of the target value;
one or more registers, coupled to the comparator, storing the lower limit of the range of the target value and the upper limit of the range of the target value;
a temperature sensor, coupled to one or more of the ADC and the one or more registers, and configured to provide temperature data to the one or more of the ADC and the registers;
the ADC further configured to adjust the digital NVM reference current value in response to the temperature data, if needed; and
the one or more registers further configured to adjust the lower limit of the range of the target value and the upper limit of the range of the target value in response to the temperature data, if needed.
2. The system of claim 1 further comprising:
an NVM program/erase controller, coupled to the trim logic and the NVM reference current generator, and configured to
receive the control signal from the trim logic,
provide an erase pulse to the generator of the NVM reference current in response to the control signal, if the control signal comprises an indicia that the digital NVM reference current value is lower than the lower limit of the range of the target value, and
provide a program pulse to the generator of the NVM reference current in response to the control signal, if the control signal comprises an indicia that the digital NVM reference current value is greater than the upper limit of the range of the target value; and
the NVM reference current generator comprises a floating gate reference bitcell.
3. The system of claim 2 wherein the NVM array comprises the floating gate reference bitcell.
4. The system of claim 1 further comprising:
a register, coupled to the ADC and the comparator, storing the digital NVM reference current value.
5. The system of claim 1 further comprising:
a control register, coupled to the trim logic and the NVM reference current generator, and configured to store a value in response to the control signal from the trim logic; and
the NVM reference generator further comprises a bandgap circuit, wherein, in response to the value stored in the control register,
the bandgap circuit is trimmed to increase the NVM reference current if the digital NVM reference current value is less than the target value range, and
the bandgap circuit is trimmed to decrease the NVM reference current if the digital NVM reference current value is greater than the target value range.
6. The system of claim 1 wherein the NVM reference current generator is disposed in proximity to the NVM array so that both are exposed to substantially similar environmental conditions.
7. The system of claim 1 wherein the ADC is further configured to perform said converting the NVM reference current to a digital NVM reference current value in response to receiving a command to initiate said converting.
8. The system of claim 1 wherein the ADC is further configured to perform said converting the NVM reference current to a digital NVM reference current value in response to one or more of a startup, power down, or a requested diagnostic check.