IP Library Granted Patent US 8,609,535
Granted Patent B2
US 8,609,535 · App. 13/286,376 · Granted Dec 17, 2013

Semiconductor package having through electrodes that reduce leakage current and method for manufacturing the same

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Quick Facts
Patent No.
US 8,609,535
App. No.
13/286,376
Granted
Dec 17, 2013
Kind
B2
Abstract

A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes.

Claims (38)

1. A method for manufacturing a semiconductor package, the method comprising:

forming through-electrodes that pass through a first surface and second surface, facing away from the first surface, of a semiconductor chip;

forming polar parts onto ends of the through-electrodes that corresponds to at least one of the first surface and the second surface and forming non-polar parts onto the at least one of the first surface and the second surface excluding the polar parts;

forming a current leakage prevention layer on the non-polar parts using a current leakage prevention substance; and

forming connection members onto at least one end of the through-electrodes.

2. The method according to claim 1 , wherein, before the step of forming the through-electrodes, the method further comprises the steps of:

defining through-holes that pass through the first and second surfaces of the semiconductor chip; and

forming an insulation layer onto inner surfaces of the semiconductor chip which are formed by the through-holes.

3. The method according to claim 2 , wherein when forming the current leakage prevention layer, the current leakage prevention layer covers exposed ends of the insulation layer.

4. The method according to claim 1 , wherein, before the step of forming the connection members, the method further comprises removing the polar parts from the ends of the through-electrodes.

5. The method according to claim 1 , wherein the step of forming the connection members comprises the steps of:

forming a nickel layer onto at least one ends of the through-electrodes; and

forming a gold layer onto the nickel layer.

6. The method according to claim 1 , wherein the step of forming the connection members comprises the steps of:

forming a copper layer onto at least one ends of the through-electrodes; and

forming an alloy layer of tin and silver onto the copper layer.

7. The method according to claim 1 , wherein the polar parts contain a hydrophilic substance, and the non-polar parts contain a hydrophobic substance.

8. The method according to claim 1 , wherein the polar parts contain a hydrophilic hydroxyl surface group (—OH).

9. The method according to claim 1 , the method further comprises the step of forming additional polar parts onto the other ends of the through-electrodes that correspond to the first surface and forming additional non-polar parts onto the first surface excluding the additional polar parts.

10. A method for manufacturing a semiconductor package, the method comprising:

forming through-electrodes that pass through a first surface and a second surface, facing away from the first surface, of a semiconductor chip;

forming non-polar parts onto ends of the through-electrodes that corresponds to at least one of the first surface and the second surface and forming polar parts onto the at least one of the first surface and the second surface excluding the non-polar parts;

forming a current leakage prevention layer on the polar parts using a current leakage prevention substance; and

forming connection members onto at least one end of the through-electrodes.

11. The method according to claim 10 , wherein, before the step of forming the through-electrodes, the method further comprises the steps of:

defining through-holes that pass through the first and second surfaces of the semiconductor chip; and

forming an insulation layer onto inner surfaces of the semiconductor chip which are formed by the through-holes.

12. The method according to claim 11 , wherein when forming the current leakage prevention layer, the current leakage prevention layer covers exposed ends of the insulation layer.

13. The method according to claim 10 , wherein, before the step of forming the connection members, the method further comprises removing the non-polar parts from the ends of the through-electrodes.

14. The method according to claim 10 , wherein the step of forming the connection members comprises the steps of:

forming a nickel layer onto at least one end of the through-electrodes; and

forming a gold layer onto the nickel layer.

15. The method according to claim 10 , wherein the step of forming the connection members comprises the steps of:

forming a copper layer onto at least one end of the through-electrodes; and

forming an alloy layer of tin and silver onto the copper layer.

16. The method according to claim 10 , wherein the non-polar parts contain any a hydrophobic substance, and the polar parts contain a hydrophilic substance.

17. The method according to claim 10 , wherein the polar parts contain a hydrophilic hydroxyl surface group (—OH).

18. The method according to claim 10 , the method further comprises the step of forming additional non-polar parts onto the other ends of the through-electrodes that correspond to the first surface and forming additional polar parts onto the first surface excluding the additional non-polar parts.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →