Semiconductor memory system and method for driving the same

1. A method for driving a semiconductor memory device, comprising:

controlling a plurality of erase voltages corresponding to a plurality of memory blocks, respectively;

comparing the plurality of controlled erase voltages with each other, wherein the comparing of the controlled erase voltages comprises detecting the erase voltage having the highest voltage level among the plurality of erase voltages; and

determining whether or not to enable the plurality of memory blocks for a subsequent write operation in response to a result of the comparison.

2. The method of claim 1 , further comprising performing a write operation on an enabled one of the memory blocks for the subsequent write operation.

3. The method of claim 1 , wherein the controlling of each of the plurality of erase voltages comprises:

reading an initial erase voltage for the corresponding memory block as the erase voltage;

controlling a voltage level of the erase voltage, while performing an erase operation on the corresponding memory block with the erase voltage; and

updating the erase voltage depending on a result of the controlling of the voltage level of the erase voltage.

4. The method of claim 1 , wherein the comparing of the controlled erase voltages comprises detecting the erase voltage having the highest voltage level among the plurality of erase voltages.

5. The method of claim 1 , wherein the memory block corresponding to the erase voltage having the highest voltage level among the plurality of erase voltages is disabled in the determining of whether or not to enable the plurality of memory blocks for subsequent write operation.

6. A semiconductor memory system comprising:

a semiconductor memory device configured to generate a plurality of final erase voltages by controlling a plurality of erase voltages corresponding to a plurality of memory blocks, respectively, and enable the plurality of memory blocks for a subsequent write operation in response to a plurality of enable control signals; and

a main control circuit configured to receive the plurality of final erase voltages from the semiconductor memory device and output the plurality of enable control signals for controlling the plurality of memory blocks in response to the plurality of final erase voltages.

7. The semiconductor memory system of claim 6 , wherein the semiconductor memory device comprises:

a plurality of voltage storage units configured to store the plurality of erase voltages, respectively; and

an erase voltage control unit configured to generate the plurality of final erase voltages by controlling the plurality of erase voltages.

8. The semiconductor memory system of claim 7 , wherein the erase voltage control unit provides the plurality of final erase voltages to the main control circuit.

9. The semiconductor memory system of claim 7 , wherein the semiconductor memory device further comprises a plurality of page buffering units configured to read the plurality of erase voltages for the respective memory blocks, transmit the read erase voltages to the erase voltage control unit, and store the plurality of final erase voltages generated by the erase voltage control unit in the respective voltage storage units.

10. The semiconductor memory system of claim 6 , wherein the main control circuit comprises:

a first storage unit configured to store data corresponding to the plurality of final erase voltages;

a second storage unit configured to store data corresponding to an initial voltage and store updated data, wherein the updated data is determined in response to a comparison result; and

a voltage comparison unit configured to compare the data of the first storage unit with the data of the second storage unit to output the comparison result.

11. The semiconductor memory system of claim 6 , wherein the enable control signals are activated in response to the final erase voltage having the highest voltage level among the plurality of final erase voltages.

12. The semiconductor memory system of claim 6 , wherein the memory block corresponding to the final erase voltage having the highest voltage level among the plurality of final erase voltages is disabled.

13. A semiconductor memory system comprising:

a semiconductor memory device comprising:

a plurality of memory blocks configured to be enabled for a subsequent write operation in response to a plurality of enable control signals;

a plurality of voltage storage units configured to store a plurality of erase voltages, respectively; and

an erase voltage control unit configured to generate a plurality of final erase voltages by controlling the plurality of erase voltages; and

a main control circuit configured to receive the plurality of final erase voltages and output the plurality of enable control signals for controlling the plurality of memory blocks in response to the plurality of final erase voltages.