IP Library Granted Patent US 8,906,218
Granted Patent B2
US 8,906,218 · App. 13/288,721 · Granted Dec 9, 2014

Apparatus and methods for uniformly forming porous semiconductor on a substrate

Inventors: Karl-Josef Kramer (San Jose, CA); Mehrdad M. Moslehi (Los Altos, CA); Subramanian Tamilmani (Milpitas, CA); George Kamian (Scotts Valley, CA); Jay Ashjaee (Cupertino, CA); Takao Yonehara (Sunnyvale, CA)
Assignee: Solexel, Inc.
C25D7/12C25F7/00C25D11/32C25D11/024
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Quick Facts
Patent No.
US 8,906,218
App. No.
13/288,721
Granted
Dec 9, 2014
Kind
B2
Abstract

This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

Claims (38)

1. A method for forming a porous semiconductor on a plurality of semiconductor wafers, said method comprising:

positioning a plurality of wafers in an array in an apparatus, said apparatus comprising:

an electrolyte-filled chamber, said chamber operable to open and close, and forming a seal when closed;

an anode disposed at a first end of said chamber;

a cathode disposed at an opposite end of said chamber, said anode and said cathode coupled to electrical circuitry capable of providing an electrical power comprising electrical voltage and current;

a plurality of semiconductor wafers arranged between said anode and said cathode, wherein each said wafer is held in place by a wafer clamp disposed around a perimeter of said wafer, said wafer clamp allowing substantially all of a front and a back surface of each said wafer exposure to said electrolyte;

a plurality of vent ports in said chamber for allowing evolved byproduct gas to escape; and

anodizing said plurality of wafers according to a pulsed anodization process, said pulsed anodization process alternating an electric current between an on and off state for a sufficient period of time to allow for the dissipation of said byproduct gas formed during anodization.

2. The method for forming a porous semiconductor on a plurality of semiconductor wafers of claim 1 , wherein said wafer clamp comprises a seal holder providing a seal between the perimeter of said wafer edge and said chamber, said seal holder supporting a plurality of pins supplying pressure to a minimal area of the bevel surface on the anodized side of said wafer and sealing said wafer to a backside flexible seal contact material.

3. The apparatus of claim 1 , wherein said semiconductor wafers are crystalline silicon wafers.

4. The apparatus of claim 1 , wherein said byproduct gas is hydrogen gas.

5. An apparatus for producing porous semiconductor on a plurality of semiconductor wafers, comprising:

an electrolyte-filled chamber, said chamber operable to open and close, and forming a seal when closed;

an anode disposed at a first end of said chamber;

a cathode disposed at an opposite end of said chamber, said anode and said cathode coupled to electrical circuitry capable of providing an electrical power comprising electrical voltage and current;

an array of a plurality of semiconductor wafers arranged between said anode and said cathode in a tunnel, said tunnel having substantially the same diameter as said wafers, each of said wafers held in place by a wafer clamp securing the surface edge of said wafer and sealing the fluid filled compartment formed between each of said wafers with said tunnel;

said anode and said cathode each having a region size smaller than the diagonal dimension of said wafer, said anode and said cathode each facing a backside wall of said chamber and away from said array of said plurality of semiconductor wafers; and

a plurality of vent holes in said chamber for allowing evolved byproduct gas to escape during anodization of said wafers.

6. The apparatus of claim 5 , wherein said backside walls of said chamber facing said anode and said cathode are shaped to create a relatively uniform electric field between said anode and said cathode.

7. The apparatus of claim 5 , further comprising transducers positioned in said electrolyte-filled chamber to dislodge byproduct gas bubbles from the surface of said wafers with sonic energy.

8. The apparatus of claim 7 , wherein said transducers are positioned to said wafer clamps.

9. The apparatus of claim 5 , wherein said electrical circuitry is operable to allow for dissipation of byproduct gas from the surface of said wafers by pulsating electrical current during anodization.

10. The apparatus of claim 5 , wherein said semiconductor wafers are crystalline silicon wafers.

11. The apparatus of claim 5 , wherein said byproduct gas is hydrogen gas.

12. The apparatus of claim 5 , wherein said wafer clamp comprises a first inner layer for minimal edge wrap-around and a second outer harder flexible layer providing a seal around said wafer edge.

13. An apparatus for producing porous semiconductor on a plurality of semiconductor wafers, comprising:

an electrolyte-filled chamber, said chamber operable to open and close, and forming a seal when closed;

an anode disposed at a first end of said chamber;

a cathode disposed at an opposite end of said chamber, said anode and said cathode coupled to electrical circuitry capable of providing an electrical power comprising electrical voltage and current;

an array of plurality of semiconductor wafers arranged between said anode and said cathode in a tunnel, said tunnel having substantially the same diameter as said wafers, each of said wafers held in place by an asymmetrical wafer clamp securing the surface edge of said wafer and sealing the fluid filled compartment formed between each of said wafers, said asymmetrical wafer clamp comprising a seal holder providing a seal between the perimeter of said wafer edge and said tunnel, said seal holder supporting a plurality of pins supplying pressure to a minimal area of the bevel surface on the anodized side of said wafer and sealing said wafer to a backside flexible seal contact material; and

a plurality of vent holes in said chamber for allowing evolved hydrogen gas to escape during anodization of said wafers.

14. The apparatus of claim 13 , wherein said asymmetrical wafer clamp further comprises a porous material positioned between said pin and said surface on the anodized side of said wafer, said porous material being fluid and electric field permeable.

15. The apparatus of claim 14 , wherein said porous material fills said fluid filled compartment.

16. The apparatus of claim 13 , further comprising transducers positioned in said electrolyte-filled chamber to dislodge byproduct gas from the surface of said wafers with sonic energy.

17. The apparatus of claim 16 , wherein said transducers are positioned to said wafer clamps.

18. The apparatus of claim 13 , wherein said electrical circuitry is operable to dislodge hydrogen gas from the surface of said wafers by pulsating electrical current during anodization.

19. The apparatus of claim 13 , wherein said semiconductor wafers are crystalline silicon wafers.

20. The apparatus of claim 13 , wherein said byproduct gas is hydrogen gas.

Assignments (10)
SECURITY INTEREST Recorded Nov 12, 2024
From: TRUTAG TECHNOLOGIES, INC.
To: KUMUKAHI HOLDINGS, INC.
Reel/Frame 069240/0893 →
NON-RECOURSE ASSIGNMENT OF INTELLECTUAL PROPERTY SECURITY AGREEMENT Recorded Oct 1, 2024
From: FIRST-CITIZENS BANK & TRUST COMPANY
To: KUMUKAHI HOLDINGS, INC.
Reel/Frame 069083/0367 →
SECURITY INTEREST Recorded Dec 26, 2023
From: TRUTAG TECHNOLOGIES, INC.
To: FIRST-CITIZENS BANK & TRUST COMPANY
Reel/Frame 066140/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 20, 2017
From: OB REALTY, LLC
To: TRUTAG TECHNOLOGIES, INC.
Reel/Frame 044920/0495 →
ASSIGNMENT OF LOAN DOCUMENTS Recorded Sep 29, 2017
From: OPUS BANK
To: OB REALTY, LLC
Reel/Frame 044062/0383 →
CHANGE OF NAME Recorded Jul 28, 2017
From: SOLEXEL, INC.
To: BEAMREACH SOLAR, INC.
Reel/Frame 043367/0649 →
RECORDATION OF FORECLOSURE OF PATENT PROPERTIES Recorded Jul 27, 2017
From: OB REALTY, LLC
To: OB REALTY, LLC
Reel/Frame 043350/0822 →
CHANGE OF NAME Recorded Jul 26, 2017
From: SOLEXEL, INC.
To: BEAMREACH SOLAR, INC.
Reel/Frame 043342/0439 →
SECURITY INTEREST Recorded Jan 7, 2015
From: SOLEXEL, INC.
To: OPUS BANK
Reel/Frame 034731/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 25, 2012
From: KRAMER, KARL-JOSEF; MOSLEHI, MEHRDAD M.; TAMILMANI, SUBRAMANIAN; KAMIAN, GEORGE D; ASHJAEE, JAY; YONEHARA, TAKAO
To: SOLEXEL, INC.
Reel/Frame 028270/0158 →
Continuity (4)
Continuation In Part 12774667 · May 5, 2010
Continuation In Part 13244466 · Sep 24, 2011
Provisional Application 61409940 · Nov 3, 2010
Related Publication 20120145553A1 · Jun 14, 2012