Power-up signal generating circuit of semiconductor integrated circuit
View Patent ↗A power-up signal generation circuit includes a discharge driving unit configured to discharge a voltage of a power-up detection node in response to a voltage of an external power supply voltage, a charge driving unit configured to charge the voltage of the power-up detection node in response to a voltage of an internal power supply voltage, a power reset discharging unit configured to discharge a voltage of the power-up detection node while the semiconductor integrated circuit is reset, and an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.
1. A power-up signal generation circuit of a semiconductor integrated circuit, comprising:
a discharge driving unit configured to discharge a voltage of a power-up detection node in response to an external power supply voltage;
a charge driving unit configured to charge the voltage of the power-up detection node in response to an internal power supply voltage;
a power reset discharging unit configured to discharge the voltage of the power-up detection node while the semiconductor integrated circuit is reset; and
an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node.
2. The power-up signal generation circuit of claim 1 , further comprising:
a temperature compensation unit configured to control a discharge driving current of the discharge driving unit in response to a temperature information.
3. The power-up signal generation circuit of claim 2 , wherein the temperature compensation unit comprises a sixth NMOS transistor having a source coupled to a terminal of a ground voltage, a drain coupled to the control node, and a gate receiving the temperature information.
4. The power-up signal generation circuit of claim 2 , further comprising a temperature detection unit configured to generate the temperature information.
5. The power-up signal generation circuit of claim 4 , wherein the temperature detection unit comprises:
a first input unit configured to divide the external power supply voltage and output the divided voltage;
a second input unit configured to output a threshold voltage for a corresponding temperature;
a comparison unit configured to compare an output signal of the first input unit with the threshold voltage of the second input unit; and
a switching unit configured to selectively output an output signal of the comparison unit as the temperature information in response to a voltage level of the power-up detection node.
6. The power-up signal generation circuit of claim 5 , wherein the first input unit comprises:
a first resistor coupled between a terminal of the external power supply voltage and a first output node;
a second resistor having one end coupled to the first output node; and
a seventh NMOS transistor having a source coupled to a terminal of the ground voltage, a drain coupled to the other end of the second resistor, and a gate receiving a temperature detection enable signal.
7. The power-up signal generation circuit of claim 6 , wherein the second input unit comprises:
a fifth PMOS transistor having a source coupled to the terminal of the external power supply voltage, a drain coupled to a second output node, and a gate coupled to the terminal of the ground voltage; and
an eighth NMOS transistor having a source coupled to the terminal of the ground voltage, and a drain and a gate coupled to the second output node.
8. The power-up signal generation circuit of claim 5 , wherein the comparison unit comprises a pseudo differential amplifier configured to receive the output signals of the first input unit and the second input unit.
9. The power-up signal generation circuit of claim 5 , wherein the switching unit comprises:
a first inverter having an input node coupled to the power-up detection node;
a transmission gate configured to selectively transfer the output signal of the comparison unit in response to an output signal of the first inverter and a signal of the power-up detection node;
a ninth NMOS transistor having a source coupled to a terminal of the ground voltage, a drain coupled to an output node of the transmission gate, and a gate coupled to the power-up detection node;
a NOR gate configured to receive signals from the transmission gate and the power-up detection node; and
a second inverter configured to receive an output signal of the NOR gate and output the temperature information.
10. The power-up signal generation circuit of claim 1 , wherein the discharge driving unit comprises:
a first PMOS transistor having a source coupled to a terminal of the external power supply voltage, a drain coupled to a control node, and a gate coupled to a terminal of a ground voltage;
a first NMOS transistor having a source coupled to the terminal of the ground voltage and a drain and a gate coupled to the control node; and
a second NMOS transistor having a source coupled to the terminal of the ground voltage, a drain coupled to the power-up detection node, and a gate coupled to the control node.
11. The power-up signal generation circuit of claim 1 , wherein the charge driving unit comprises:
a second PMOS transistor having a source coupled to a terminal of the internal power supply voltage and a drain and a gate coupled to a first node; and
a third PMOS transistor having a source coupled to the first node, a drain coupled to the power-up detection node, and a gate coupled to a terminal of a ground voltage.
12. The power-up signal generation circuit of claim 1 , wherein the power reset discharging unit comprises:
a third NMOS transistor having a drain coupled to the power-up detection node and a gate coupled to a terminal of the external power supply voltage;
a fourth PMOS transistor having a source coupled to a source of the third NMOS transistor and a gate coupled to the terminal of the external power supply voltage;
a fourth NMOS transistor having a source coupled to a terminal of a ground voltage, a drain coupled to a drain of the fourth PMOS transistor, and a gate coupled to the terminal of the external power supply voltage;
a fifth NMOS transistor having a source coupled to the terminal of the ground voltage, a drain coupled to the power-up detection node, and a gate coupled to the drain of the fourth NMOS transistor; and
a capacitor coupled between the source of the third NMOS transistor and the terminal of the ground voltage.
13. The power-up signal generation circuit of claim 1 , wherein the output unit comprises:
a third inverter having an input node coupled to the power-up detection node;
a sixth PMOS transistor having a source coupled to a terminal of the internal power supply voltage, a drain coupled to the power-up detection node, and a gate coupled to an output node of the third inverter; and
a fourth inverter configured to receive an output signal of the third inverter and output the power-up signal.
14. The power-up signal generation circuit of claim 1 , wherein the output unit comprises:
a fifth inverter having an input node coupled to the power-up detection node;
a sixth inverter configured to receive an output signal of the fifth inverter and output the power-up signal; and
a seventh inverter having an input node coupled to an output node of the fifth inverter and an output node coupled to the power-up detection node.
15. The power-up signal generation circuit of claim 1 , wherein the output unit comprises:
a eighth inverter having an input node coupled to the power-up detection node; and
a ninth inverter configured to receive an output signal of the eighth inverter and output the power-up signal.
16. A power-up signal generation circuit of a semiconductor integrated circuit, comprising:
a discharge driving unit configured to discharge a voltage of a power-up detection node in response to an external power supply voltage;
a charge driving unit configured to charge the voltage of the power-up detection node in response to an internal power supply voltage;
an output unit configured to output a power-up signal in response to a voltage change of the power-up detection node; and
a temperature compensation unit configured to raise a discharge driving voltage of the discharge driving unit in response to a temperature information while the semiconductor integrated circuit is reset,
wherein the temperature compensation unit comprises a third NMOS transistor having a source coupled to a terminal of a around voltage, a drain coupled to the control node, and a gate receiving the temperature information.
17. The power-up signal generation circuit of claim 16 , wherein the discharge driving unit comprises:
a first PMOS transistor having a source coupled to a terminal of the external power supply voltage, a drain coupled to a control node, and a gate coupled to a terminal of a ground voltage;
a first NMOS transistor having a source coupled to the terminal of the ground voltage, a drain and a gate coupled to the control node; and
a second NMOS transistor having a source coupled to the terminal of the ground voltage, a drain coupled to the power-up detection node, and a gate coupled to the control node.
18. The power-up signal generation circuit of claim 16 , further comprising a temperature detection unit configured to generate the temperature information.
19. The power-up signal generation circuit of claim 18 , wherein the temperature detection unit comprises;
a first input unit configured to divide the external power supply voltage and output the divided voltage;
a second input unit configured to output a threshold voltage for a corresponding temperature;
a comparison unit configured to compare an output signal of the first input unit with the threshold voltage of the second input unit; and
a switching unit configured to selectively output an output signal of the comparison unit as the temperature information in response to a level of the power-up detection node.
20. A power-up signal generation circuit of a semiconductor integrated circuit, comprising:
a power supply voltage detection unit configured to detect an external power supply voltage and an internal power supply voltage and generate a power-up signal,
wherein the power supply voltage detection unit is configured to generate the power-up signal with a driving voltage charged and discharged in response to the internal and external power supply voltages, respectively;
a temperature compensation unit configured to control the driving voltage in response to a temperature information; and
a power reset discharging unit configured to discharge the driving voltage in response to the external power supply voltage.