Method of packaging semiconductor die
View Patent ↗A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.
1. A method of packaging a semiconductor die, comprising:
providing a process mounting surface having an encapsulating area;
placing an embedded unit on the process mounting surface within the encapsulating area, wherein the embedded unit has a first surface, an inner surface and an outer surface, the first surface having a first opening defined by the inner surface through the embedded unit, and wherein the first surface is positioned on the process mounting surface for forming a first cavity;
placing a first semiconductor die on the process mounting surface, wherein the first semiconductor die has electrical contacts for electrical connection with external circuitry, wherein the first semiconductor die is located within the first cavity such that the embedded unit inhibits movement of the first semiconductor die, wherein the first surface of the embedded unit has at least two openings therethrough, wherein the at least two openings have different dimensions;
placing a second semiconductor die in a second cavity formed by a second opening; and
covering the inner and outer surfaces of the embedded unit and the first and second semiconductor dies with an encapsulation material, thereby forming a packaged semiconductor device.
2. The method of packaging a semiconductor die of claim 1 , wherein the process mounting surface is a substrate, and further comprising removing the process mounting surface to expose the electrical contacts of the first semiconductor die.
3. The method of packaging a semiconductor die of claim 1 , wherein the process mounting surface comprises a surface on a layer within the packaged semiconductor device.
4. The method of packaging a semiconductor die of claim 1 , further comprising:
placing at least two, separate embedded units on the process mounting surface and within the encapsulating area; and
placing at least one semiconductor die within each cavity of each embedded unit, and wherein the first surface of each of the at least two embedded units are spaced apart on the process mounting surface and separated by encapsulation material.
5. The method of packaging a semiconductor die of claim 4 , further comprising forming at least two packaged semiconductor devices from the at least two embedded units without penetrating the at least two embedded units.
6. The method of packaging a semiconductor die of claim 4 , wherein the at least two embedded units have different dimensions and are formed of different materials.
7. The method of packaging a semiconductor die of claim 1 , wherein placing of the first semiconductor die on the process mounting surface occurs before placing the embedded unit on and within the encapsulating area of the process mounting surface.
8. The method of packaging a semiconductor die of claim 1 , further comprising:
placing at least two embedded units within the encapsulating area on the process mounting surface, wherein each of the at least two embedded units are joined;
placing at least one semiconductor die within each cavity of each embedded unit; and
removing material from between each adjacent embedded unit of the at least two embedded units to form a gap and separate the embedded units such that the first surfaces of each of the at least two embedded units are spaced apart on the process mounting surface and each of the at least two embedded units are separate and unjoined.
9. A packaged integrated circuit, comprising:
a process mounting surface plane;
an embedded unit having a first surface, at least two inner surfaces and an outer surface, the first surface having at least two openings through the embedded unit, wherein the at least two openings have different dimensions defined by the at least two inner surfaces, and the first surface on the process mounting surface plane;
at least two integrated circuits each having a first surface and a second surface, the first surface of each of the integrated circuits on the process mounting surface plane, the integrated circuits respectively positioned within the at least two openings defined by the at least two inner surfaces of the embedded unit, the at least two integrated circuits having electrical contacts for electrical connection with external circuitry, the embedded unit and the at least two integrated circuits arranged to inhibit movement of the at least two integrated circuits during encapsulation; and
an encapsulation material covering at least a portion of the outer surface of the embedded unit, the at least two inner surfaces of the embedded unit, and the second surface of each of the integrated circuits for forming the packaged integrated circuit.
10. The packaged integrated circuit of claim 9 , wherein the process mounting surface plane is formed by a temporary surface that is removed to expose the electrical contacts of the integrated circuits.
11. The packaged integrated circuit of claim 10 , wherein the temporary surface is a substrate, panel, or tape.
12. The packaged integrated circuit of claim 9 , wherein the packaged integrated circuit comprises at least two layers and the process mounting surface plane is formed by a surface on a layer within the packaged integrated circuit.
13. The packaged integrated circuit of claim 9 , further comprising:
at least two embedded units on the process mounting surface plane, wherein each outer surface of the at least two embedded units are separated by encapsulating material;
at least one integrated circuit is disposed on the process mounting surface plane within each cavity each embedded units; and
each integrated circuit is separated by encapsulating material from the inner surface of each respective embedded unit.
14. The packaged integrated circuit of claim 9 , wherein the packaged integrated circuit is formed from a single process mounting surface plane comprising at least two embedded units and singulated to form at least two integrated circuit packaged assemblies without penetrating any part of any one of the at least two embedded units.
15. The packaged integrated circuit of claim 9 , further comprising at least two embedded units, each embedded unit having different dimensions and materials.
16. An embedded unit for a packaged integrated circuit, the embedded unit comprising:
a body having a first surface, at least two inner surfaces, and an outer surface, wherein the first surface has at least two openings that extend through the embedded unit, wherein the two openings have different dimensions defined by the at least two inner surfaces;
wherein the first surface is positioned on a process mounting surface within an encapsulating area for forming at least two cavities each to receive a semiconductor die on the process mounting surface;
wherein the outer surface and the at least two inner surfaces are for being encapsulated by an encapsulant material; and
wherein the embedded unit reduces movement of the semiconductor die on a process mounting surface during encapsulation.