Package for three dimensional integrated circuit
A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.
1. A device comprising:
a semiconductor substrate having a recess portion and a non-recess portion, wherein a first recess is located at the recess portion;
an isolation layer formed on the non-recess portion of the semiconductor substrate;
a redistribution layer formed on the isolation layer;
an under bump metal structure formed on the redistribution layer; and
a first bump formed on the under bump metal structure.
2. The device of claim 1 , wherein the first recess is of a step shape at a first side of the device.
3. The device of claim 2 , further comprising:
a second recess having the step shape at a second side of the device; and
a third recess having the step shape at a third side of the device.
4. The device of claim 2 , further comprising:
a second recess having the step shape at a second side of the device.
5. The device of claim 1 , wherein the first recess is of a slope shape.
6. The device of claim 1 , wherein the first recess is of a curved shape.
7. A device comprising:
a first semiconductor die having
a first semiconductor substrate having a first recess portion, a first top non-recess portion and a first side non-recess portion, wherein a first step recess is located at the first recess portion;
a first isolation layer formed on the first top non-recess portion of the first semiconductor substrate; and
a first bump formed on the first isolation layer;
a second semiconductor die having
a second semiconductor substrate having a second recess portion, a second top non-recess portion and a second side non-recess portion, wherein a second step recess is located at the second recess portion;
a second isolation layer formed on the second top non-recess portion of the second semiconductor substrate; and
a second bump formed on the second isolation layer;
a package substrate having
a first side coupled to the first bump of the first semiconductor die and the second bump of the second semiconductor die;
a second side having a third bump; and
an underfill layer formed between the first semiconductor die, the second semiconductor die and the package substrate, wherein the first top non-recess portion, the first recess portion, the second top non-recess portion and the second recess portion are embedded in the underfill layer.
8. The device of claim 7 , wherein:
the first semiconductor substrate is coupled to the package substrate using a plurality of first bumps; and
the second semiconductor substrate is coupled to the package substrate using a plurality of second bumps.
9. The device of claim 7 , further comprising:
a compound layer formed on the package substrate, wherein the first semiconductor die and the second semiconductor die are embedded in the compound layer.
10. The device of claim 7 , wherein the package substrate comprises a plurality of vias.
11. The device of claim 7 , further comprising:
an isolation layer formed on the second side of the package substrate; and
a redistribution layer formed on the isolation layer.
12. The device of claim 11 , further comprising:
an under bump metal structure formed on the redistribution layer; and
the third bump formed on the under bump metal structure.
13. The device of claim 7 , wherein:
the first step recess has a vertical depth in a range from about 20 um to about 300 um; and
the second step recess has a vertical depth in a range from about 20 um to about 300 um.
14. The device of claim 7 , wherein:
the first step recess has a horizontal length in a range from about 20 um to about 200 um; and
the second step recess has a horizontal length in a range from about 20 um to about 200 um.