IP Library Granted Patent US 8,597,983
Granted Patent B2
US 8,597,983 · App. 13/299,564 · Granted Dec 3, 2013

Semiconductor device packaging having substrate with pre-encapsulation through via formation

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Quick Facts
Patent No.
US 8,597,983
App. No.
13/299,564
Granted
Dec 3, 2013
Kind
B2
Abstract

A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Claims (39)

1. A method for packaging an electronic device assembly, the method comprising:

providing a printed circuit substrate having an interconnect;

forming one or more signal conduits on the printed circuit substrate, wherein

a first end of each signal conduit contacts a conductive pad on a major surface of the printed circuit substrate, and

the conductive pad is coupled to the interconnect;

forming an encapsulant over and around sides of the one or more signal conduits, wherein said forming the encapsulant is performed subsequent to said forming the one or more signal conduits; and

exposing a second end of each signal conduit of the one or more signal conduits, wherein each signal conduit forms a conductive via through the electronic device assembly.

2. The method of claim 1 wherein said forming the one or more signal conduits comprises:

forming a photoresist layer over the printed circuit substrate;

forming one or more openings in the photoresist layer corresponding to where the one or more signal conduits are desired;

depositing a conductive material in the openings in the photoresist layer; and

stripping the photoresist layer from the printed circuit substrate.

3. The method of claim 2 further comprising:

performing an under bump metallization on one or more of the one or more signal conduits, wherein said under bump metallization is performed prior to said forming the encapsulant.

4. The method of claim 1 wherein said exposing the second end of each signal conduit comprises controlling said forming the encapsulant to a thickness less than or equal to a length of the signal conduits.

5. The method of claim 1 wherein said exposing the second end of each signal conduit comprises laser ablating the encapsulant from an area around the second end of each signal conduit.

6. The method of claim 1 further comprising:

placing a first electronic device on the printed circuit substrate in an area for the electronic device assembly, wherein

said forming the encapsulant further comprises forming the encapsulant over and around sides of the first electronic device.

7. The method of claim 6 further comprising:

electrically coupling the first electronic device to the interconnect prior to said forming the encapsulant.

8. The method of claim 7 wherein said electrically coupling comprises forming a wire bond from a contact pad of the first electronic device to a wire bond pad formed on the major surface of the printed circuit substrate.

9. The method of claim 7 wherein said electrically coupling comprises contacting a conductive pad of the first electronic device to a pad formed on the major surface of the printed circuit substrate.

10. The method of claim 1 further comprising:

placing a second electronic device assembly on the exposed second end of one or more signal conduits such that the second electronic device assembly is electrically coupled to the one or more signal conduits.

11. A method for packaging an electronic device assembly, the method comprising:

forming a photoresist layer on a printed circuit substrate;

forming one or more openings in the photoresist layer, wherein the one or more openings extend from the surface of the photoresist layer to contacts on the printed circuit substrate;

depositing a conductive material in the openings in the photoresist layer to form corresponding one or more signal conduits;

stripping the photoresist layer from the printed circuit substrate and the signal conduits; and

forming an encapsulant over and around sides of the one or more signal conduits and over the printed circuit substrate; and

exposing an end of the one or more signal conduits, wherein said exposing the end comprises removing a portion of the encapsulant from the electronic device assembly.

12. The method of claim 11 further comprising:

placing an electronic device on the printed circuit substrate in an area for the electronic device assembly, after said stripping the photoresist layer from the printed circuit substrate; and

forming the encapsulant over and around sides of the electronic device.

13. The method of claim 11 wherein said removing the portion of the encapsulant comprises one of:

laser ablating the encapsulant from the electronic device assembly to a depth at least matching the end of the signal conduits,

grinding the encapsulant from the electronic device assembly to a depth at least matching the end of the signal conduits, or

etching the encapsulant from the electronic device assembly to a depth at least matching the end of the signal conduits.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0439 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0379 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0447 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0967 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027821/0662 →