Granted Patent B2

US 9,041,209 · App. 13/299,566 · Granted May 26, 2015

Abstract

Claims (25)

1. A method for tiling selected vias in a semiconductor device having a plurality of vias, the method comprising:

generating a layout database for the semiconductor device;

creating zones around the plurality of vias by upsizing the plurality of vias;

measuring density of covering metal in each created zone, wherein the covering metal in each created zone is located in a metal layer that is above the plurality of vias;

selecting a low density zone as being a zone of the created zones that has a covering metal density less than a threshold metal density; and

adding at least one tiling feature on the metal layer above the plurality of vias in the low density zone so that the covering metal density of the low density zone increases to at least the same as the threshold metal density.

2. The method of claim 1 , wherein creating the zones comprises:

creating the zones by upsizing the plurality of vias.

3. The method of claim 1 , wherein adding tiling features on the metal layer, further comprises the metal layer being an inlaid metal layer.

4. The method of claim 1 , wherein the creating zones comprises upsizing the vias a predetermined amount based on an original size of the vias.

5. The method of claim 1 , wherein creating zones comprises defining the zones to have a dimension no larger than an order of magnitude of twice the minimum metal feature size for the semiconductor device.

6. The method of claim 1 , wherein adding the tiling feature further comprises adding tiling features to obtain a metal coverage of no less than 3 percent of surface area within the zone.

7. The method of claim 1 , wherein the method is performed for interlevel dielectric layers of the semiconductor device comprising a low-k oxide.

8. The method of claim 1 , wherein creating the zones around the vias further comprises upsizing the vias by 0.9 microns per side.

9. A method for tiling selected vias in a semiconductor device having a plurality of vias, the method comprising:

generating a layout database for the semiconductor device;

creating a plurality of zones by upsizing the plurality of vias;

disregarding zones of the plurality of zones that have more than a threshold metal density of covering metal as being not low density zones, wherein the covering metal is located in a metal layer located above the plurality of vias;

selecting zones in remaining zones of the plurality of zones as being low density zones; and

adding at least one tiling feature on the metal layer in each of the low density zones.

10. The method of claim 9 wherein creating the plurality of zones further comprises defining the zones as being no larger than an order of magnitude of twice the minimum metal feature size for the semiconductor device.

11. The method of claim 9 , further comprising selecting dimensions of polygons used to pattern trenches for metallization such that the at least one tiling feature is capable of fitting into an existing layout and meet a density goal of greater than 20% in the remaining zones.

12. The method of claim 9 , wherein creating the plurality of zones further comprises sizing the zones to be no greater than twelve times a minimum pitch between metal lines for the semiconductor device.

13. The method of claim 9 , wherein adding at least one tiling feature further comprises adding tiling features to obtain a metal coverage of no less than five percent of surface area within the remaining zones.

14. The method of claim 9 , wherein the method is performed for interlevel dielectric layers of the semiconductor device comprising a low-k oxide.

Assignments (20)