Semiconductor memory device having a floating body capacitor, memory cell array having the same and method of manufacturing the same

1. A semiconductor memory device comprising:

an SOI substrate with a base substrate on which a conducting surface, a buried insulating layer and a device-forming layer are stacked;

a switching transistor formed in a portion of the device-forming layer, having a gate, a source region and a drain region; and

a storage capacitor formed by the buried insulating layer, the conducting surface of the base substrate, and accumulated holes generated in an active area of the device-forming layer,

a contact plug that penetrates the device-forming layer and the buried insulating layer and is in contact with the conducting surface of the base substrate,

wherein the storage capacitor is electrically connected between a body of the switching transistor and a bias line, and charged or discharged in response to a driving of the switching transistor, and

wherein the portion of the device layer is insulated from an isolation layer and the buried insulating layer, and the contact plug is formed outside the isolating layer and the portion of the device-forming layer.

2. The semiconductor memory device of claim 1 , wherein the base substrate having the conducting surface includes a conductive well formed in the base substrate, and wherein a variable bias voltage is applied to the conductive well.

3. The semiconductor memory device of claim 1 , wherein the base substrate having the conducting surface includes a conducting layer, and wherein the conducting layer transmits an electrical signal.

4. The semiconductor memory device of claim 1 , wherein sidewalls of the contact plug are contacted with an active area of the device-forming layer,

wherein the active area is an area which is formed in one memory cell constituted of the switching transistor and the storage capacitor.

5. The semiconductor memory device of claim 1 , wherein the body of the switching transistor corresponds to the active area which is between the source region and the drain region.

6. The semiconductor memory device of claim 1 , wherein the switching transistor is a fully depleted transistor.

7. The semiconductor memory device of claim 1 , wherein the switching transistor is a partially depleted transistor.

8. The semiconductor memory device of claim 1 , wherein the switching transistor has the gate connected with a word line, the source region connected with a ground terminal and drain region connected with a bit line.

9. A method for forming a semiconductor memory device comprising:

providing an SOI substrate, wherein the SOI substrate includes a base substrate having a conducting surface, a buried insulating layer and a device-forming layer;

forming a transistor having a gate, a source region and a drain region on the SOI substrate; and

forming a contact plug in contact with the conducting surface of the base substrate, wherein sidewalls of the contact plug are contacted with an area of the device-forming layer, and an adjustable bias voltage is applied to the contact plug,

wherein a storage capacitor is formed by connecting between the conducting surface and the active area, formed by the buried insulating layer, the conducting surface and accumulated holes generated in the active area, and

wherein the contact plug is formed outside of the source region and the drain region.

10. The method claim 9 , wherein the providing of the SOI substrate includes:

preparing the base substrate having the conducting surface;

preparing an attachment substrate in which the buried insulating layer is formed; and

planarizing a surface of the attachment substrate and forming the device-forming layer is formed.

11. The method of claim 9 , wherein the preparing of the base substrate having the conducting surface includes forming a conducting layer on the base substrate.

12. The method of claim 9 , wherein the transistor has the gate connected with a word line, the source region connected with a ground terminal and a drain region connected with a bit line.

13. The method claim 11 , wherein forming the conducting layer comprises forming a conductive well in the base substrate.

14. A memory cell array of the semiconductor memory device comprising:

a plurality of word lines;

a plurality of bit lines arranged to intersect with the plurality of the word lines, respectively; and

a plurality of memory cells formed in respective points of intersection of the plurality of word lines with the plurality of bit lines, respectively;

wherein one of the memory cells includes a switching transistor having a gate connected with one of the word lines, a source region connected with a ground terminal and a drain region connected with one of the bit lines, and a storage capacitor connected between a body of the switching transistor and a bias line,

wherein the storage capacitor is formed by a buried insulating layer formed under the active area, a conducting surface formed under the buried insulating layer and accumulated holes generated in the active area, and

wherein a contact plug is formed outside the drain region and a source region.