Methods and apparatus to improve reliability of isolated vias
View Patent ↗A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
1. A method for increasing metal density around selected vias in a semiconductor device having a plurality of vias, the method comprising:
generating a layout database for the semiconductor device;
identifying isolated vias of the plurality of vias;
selecting the isolated vias;
defining a zone around each of the selected isolated vias; and
increasing area of a metal line which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone.
2. The method of claim 1 , wherein identifying isolated vias further comprises:
creating a plurality of polygon shapes by upsizing the plurality of vias; and
identifying an isolated via as being a via within a polygon shape that has not been merged with another polygon shape.
3. The method of claim 1 , wherein increasing area of the metal line above and around the selected isolated vias within the zone, further comprises the metal line being an inlaid metal line.
4. The method of claim 1 , wherein defining a zone further comprises upsizing the selected isolated vias a predetermined amount based on an original size of the isolated vias.
5. The method of claim 1 , wherein defining a zone around each of the selected isolated vias further comprises defining the zone to have a dimension no larger than an order of magnitude of a minimum metal feature size for the semiconductor device.
6. The method of claim 1 , wherein identifying isolated vias of the plurality of vias further comprises identifying isolated vias to be vias having no other vias within two times a minimum pitch between metal lines for the semiconductor device.
7. The method of claim 1 , wherein increasing area of a metal line above and around the selected isolated via within each zone achieves a target metal density of at least 10 percent within the zone.
8. The method of claim 1 , wherein the method is performed for interlevel dielectric layers of the semiconductor device comprising a low-k oxide.
9. The method of claim 1 , wherein defining a zone around each of the selected isolated vias further comprises upsizing the selected isolated vias by 0.9 microns per side.
10. The method of claim 1 , wherein increasing area of a metal line above and around the selected isolated via within each zone achieves a target metal density of at least 10 percent within the zone.
11. A method for increasing metal density around selected vias in a semiconductor device having a plurality of vias, the method comprising:
generating a layout database for the semiconductor device;
creating a plurality of polygon shapes by upsizing the plurality of vias;
discounting polygon shapes of the plurality of polygon shapes that enclose more than one via as being not isolated;
selecting vias in remaining polygon shapes as being isolated vias;
temporarily upsizing the selected vias by a predetermined amount based on an original size of the selected vias; and
within a space enclosed by each upsized selected via, expanding a metal line which is above the selected via and which encloses the selected via to achieve a target metal density within the space.
12. The method of claim 11 wherein expanding a metal line within a space enclosed by each upsized selected via further comprises defining the space enclosed by each upsized selected via as being no larger than an order of magnitude of a minimum metal feature size for the semiconductor device.
13. The method of claim 11 , wherein expanding a metal line within a space enclosed by each upsized selected via achieves a target metal density of at least 10 percent within the space.
14. The method of claim 11 , wherein selecting vias in remaining polygon shapes as being isolated vias further comprises sizing the polygon shapes to be no greater than two times a minimum pitch between metal lines for the semiconductor device.
15. The method of claim 11 , wherein expanding a metal line within a space enclosed by each upsized selected via achieves a target metal density of at least 20 percent within the space.
16. The method of claim 11 , wherein the method is performed for interlevel dielectric layers of the semiconductor device comprising a low-k oxide.