Method and system for auto-ranging analog-to-digital converter for current sensing
View Patent ↗Embodiments of the present disclosure provide a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to an ADC. The auto-ranging ADC includes a dynamically configurable transistor arrangement for delivering a load current and a replica device for replicating the load current. A current sense resistor generates a replicated load voltage based on the replicated current. The ADC generates a digital value based on the replicated load voltage. The auto-ranging ADC also includes an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.
1. An auto-ranging system for dynamically scaling inputs to an analog-to-digital converter, the auto-ranging system comprising:
a dynamically configurable transistor arrangement for providing a load current;
a replica device for replicating the load current and generating a replicated load voltage based on the replicated current;
an analog-to-digital converter for generating a digital value based on the replicated load voltage; and
an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the analog-to-digital converter.
2. The auto-ranging system of claim 1 , further comprising an anti-aliasing filter for restricting frequency bandwidth of the replicated load voltage.
3. The auto-ranging system of claim 1 , further comprising a current mirror for mirroring the replicated load current.
4. The auto-ranging system of claim 1 , further comprising a current sense resistor for generating the replicated load voltage based on the replicated current.
5. The auto-ranging system of claim 1 , wherein the transistor arrangement includes at least three transistors connected in parallel to each other.
6. The auto-ranging system of claim 5 , wherein a state of a transistor is switched to dynamically configure of the transistor arrangement.
7. The auto-ranging system of claim 1 , wherein the auto-ranging controller includes a memory device for storing a threshold value of the digital value for determining the configuration of the transistor arrangement.
8. The auto-ranging system of claim 7 , wherein the memory device is a one-time programmable memory.
9. The auto-ranging system of claim 7 , wherein the memory device stores a switching table for determining a state of switches which change the configuration of transistor arrangement.
10. The auto-ranging system of claim 1 , wherein the analog-to-digital converter is an 8-bit successive-approximation-register (SAR) analog-to-digital converter (ADC).
11. An auto-ranging method for dynamically scaling inputs to an analog-to-digital converter, the auto-ranging method comprising:
providing a load current by a dynamically configurable transistor arrangement;
replicating the load current;
generating a replicated load voltage based on the replicated current;
generating a digital value based on the replicated load voltage by the analog-to-digital converter; and
dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the analog-to-digital converter.
12. The auto-ranging method of claim 11 , further comprising filtering the replicated load voltage to restrict frequency bandwidth of the replicated load voltage.
13. The auto-ranging method of claim 11 , further comprising mirroring the replicated load current by a current mirror.
14. The auto-ranging method of claim 11 , wherein the transistor arrangement includes at least three transistors connected in parallel to each other.
15. The auto-ranging method of claim 14 , further comprising switching a state of a transistor to dynamically configure of the transistor arrangement.
16. The auto-ranging method of claim 11 , further comprising determining the configuration of the transistor arrangement based on a threshold value of the digital value.
17. The auto-ranging method of claim 11 , further comprising determining a state of switching signals from a switching table for a configuration of the transistor arrangement.