COMPUTER SYSTEMS AND METHODS FOR REGISTER-BASED MESSAGE PASSING
Systems and methods are disclosed that include a plurality of processing units having a plurality of register file entries. Control logic identifies a first register entry as including a message address in response to receiving a first instruction. The control logic further identifies a second register entry to receive messages in response to receiving a second instruction.
1 . A computer processing system comprising:
a plurality of processing units including a plurality of register file entries;
control logic operable to:
identify a first register entry as including a message address in response to receiving a first instruction; and
identify a second register entry to receive messages in response to receiving a second instruction.
2 . The system of claim 1 further comprising:
a plurality of interconnect nodes, each of the interconnect nodes communicate with a respective one of the processing units and to neighboring interconnect nodes and configured with a corresponding interconnect address; and
each of the messages including a destination address, wherein the interconnect nodes deliver the messages to the respective one of the processing units when the message destination address matches the interconnect node address.
3 . The system of claim 1 further comprising:
a plurality of interconnect nodes, each of the interconnect nodes communicate with a respective one of the processing units and to neighboring interconnect nodes and configured with a corresponding interconnect address; and
the processing units, the interconnect addresses and the destination addresses correspond to a Cartesian coordinate system, wherein
the interconnect nodes deliver the messages to a respective one of the processing units when the coordinates of the interconnect match the coordinates of the destination address;
the interconnect nodes route the messages to another interconnect with a greater y-coordinate when the y-coordinate of the destination addresses is greater than the y-coordinate of the interconnect address;
the interconnect nodes route the messages to another interconnect with a lesser y-coordinate when the y-coordinate of the destination addresses is less than the y-coordinate of the interconnect address;
the interconnect nodes route the messages to another interconnect node with a greater x-coordinate when the x-coordinate of the destination addresses is greater than the x-coordinate of the interconnect node address; and
the interconnect nodes route the messages to another interconnect node with a lower x-coordinate when the x-coordinate of the destination addresses is less than the x-coordinate of the interconnect node address.
4 . The system of claim 1 further comprising:
each of a plurality of messages includes a source address, a destination address, destination coordinates, source coordinates, a receive register specifying field, and message data.
5 . The system of claim 2 further comprising:
a first buffer between each of the plurality of interconnect nodes and processing units configured to store messages to be delivered to the respective one of the processing units; and
a second buffer between each of the plurality of interconnect nodes and processing units configured to store messages to be sent by the respective one of the processing units.
6 . The system of claim 1 wherein
if one of the plurality of interconnect nodes cannot deliver a message to a respective processing unit, the one of the plurality of interconnects:
sends a new message back to a processing unit that sent the message, wherein the new message includes a source address that is the destination address to which the message could not be delivered, a destination address that is the source address of the message that could not be delivered, and the data in the message; and
sets a tag value in the new message indicating the message was not delivered.
7 . The system of claim 1 further comprising:
a first interconnect node in the plurality of interconnect nodes sending a message is configured to request buffer space for messages from the first interconnect node from a second interconnect node in the plurality of interconnect nodes receiving the message; and
the second interconnect node responds to the request for buffer space from the first interconnect node by indicating how much of the buffer space has been allocated for the messages from the first interconnect node.
8 . The system of claim 1 further comprising:
control logic operable to send an indication of how much buffer space is being used by each of the processing units that has requested buffer space when a predetermined amount of the buffer space is being used.
9 . The system of claim 1 further comprising:
control logic operable to:
clear the first register entry to not include the message address in response to receiving a third instruction (clearforsend); and
clear the second register entry to not receive messages in response to receiving a fourth instruction (clearforreceive).
10 . The system of claim 1 further comprising:
the first and second register entries include a sender indicator, a receiver indicator, and a message indicator, wherein
executing a first instruction sets the sender indicator of a specified register entry;
executing a third instruction clears the sender indicator for the specified register entry;
executing a second instruction sets the receiver and message indicators for the specified register entry; and
executing a fourth instruction clears the receiver indicator for the specified register entry.
11 . A computer processing system comprising:
a plurality of processing units configured to communicate messages among the processing units; and
a plurality of registers, wherein the registers are accessible by the processing units and each of the registers includes an indicator of whether the register is a message sender or a message receiver.
12 . The computer processing system of claim 11 wherein
registers include an indicator of whether a message is available.
13 . The computer processing system of claim 11 further comprising:
a destination of a message is specified as an address in a register in a sending processing unit.
14 . The computer processing system of claim 13 further comprising:
the message is received in a register in a receiving processing unit.
15 . The computer processing system of claim 11 further comprising:
a plurality of interconnect nodes, each of the interconnect nodes communicate with a respective one of the processing units and is configured with a corresponding interconnect address; and
the processing units, the interconnect addresses and the destination addresses correspond to a coordinate system, wherein the interconnects deliver the messages to a respective one of the processing units when coordinates of the interconnect match coordinates of the destination address.
16 . The computer processing system of claim 11 , wherein the control logic is further operable to perform at least one of the group consisting of:
send one of the messages to multiple destinations, and
utilize multithreading capabilities in the processing units.
17 . The computer processing system of claim 11 , wherein the control logic is further operable to:
perform a rendezvous action awaiting messages which will arrive in an unknown order.
18 . The computer processing system of claim 11 , wherein the control logic is further operable to:
send messages between agents other than the plurality of processing units.
19 . A method comprising:
determining whether a register associated with a processing unit in a computer processing system is marked as a receive register and includes a message;
if the register is marked as a receive register and includes a message, a value in the register is available to use as an operand to execute an instruction;
determining whether a register in the computer processing system is marked as a send register;
if the register is marked as a send register, then a result of an operation is sent over an interconnect to another register specified by a value in the send register; and
determining whether all operands for an instruction are available;
if all of the operands are available, executing the instruction.
20 . The method of claim 19 , further comprising:
if all of the operands are not available, performing at least one of the group consisting of:
stalling execution of the instruction, resetting an instruction pointer to point at the stalled instruction, and reattempting to execute the stalled instruction during a subsequent processor cycle; and
stalling execution of the instruction until all the operands are available.