Logic and non-volatile memory (NVM) integration
View Patent ↗A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.
1. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a gate dielectric layer over the substrate in the NVM region and the logic region;
forming a first conductive layer over the gate dielectric layer in the NVM region and the logic region;
patterning the first conductive layer in the NVM region to form a select gate while maintaining the first conductive layer in the logic region;
forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region;
forming a second conductive layer over the charge storage layer in the NVM region and the logic region;
removing the second conductive layer and the charge storage layer from the logic region while maintaining the second conductive layer and the charge storage layer in the NVM region;
patterning the first conductive layer in the logic region to form a first logic gate; and
after the patterning the first conductive layer in the logic region to form the first logic gate, patterning the second conductive layer and the charge storage layer in the NVM region to form a control gate which overlaps a first sidewall of the select gate.
2. The method of claim 1 , wherein after the patterning the first conductive layer in the logic region to form the first logic gate and prior to the patterning the second conductive layer in the NVM region to form the control gate, the method further comprises:
forming a second gate dielectric layer over the second conductive layer in the NVM region and the first logic gate in the logic region;
forming a third conductive layer over the second gate dielectric layer in the NVM region and the logic region;
patterning the third conductive layer to remove the third conductive layer and the second gate dielectric layer from the NVM region and to form a second logic gate in the logic region, wherein the first logic gate corresponds to a first transistor having a first conductivity type and the second logic gate corresponds to a second transistor having a second conductivity type, opposite from the first conductivity type.
3. The method of claim 2 , further comprising:
forming source/drain regions in the substrate adjacent a second sidewall of the select gate and adjacent a sidewall of the control gate;
forming source/drain regions in the substrate adjacent sidewalls of the first logic gate; and
forming source/drain regions in the substrate adjacent sidewalls of the second logic gate.
4. The method of claim 1 , further comprising:
forming source/drain regions in the substrate adjacent a second sidewall of the select gate and adjacent a sidewall of the control gate; and
forming source/drain regions in the substrate adjacent sidewalls of the first logic gate.
5. The method of claim 1 , wherein the step forming the gate dielectric layer comprises forming a high-k dielectric layer and the step of forming the first conductive layer comprises forming a first metal layer.
6. The method of claim 5 , wherein the step of forming the charge storage layer comprises:
forming a bottom high-k dielectric layer over the select gate in the NVM region and the first conductive layer in the logic region;
forming a plurality of nanocrystals over the bottom high-k dielectric layer in the NVM region and the logic region; and
forming a top high-k dielectric layer over the plurality of nanocrystals in the NVM region and the logic region.
7. The method of claim 6 , wherein the step of forming the plurality of nanocrystals comprises forming a plurality of metal nanocrystals.
8. The method of claim 1 , wherein the step of patterning the first conductive layer in the NVM region to form a select gate while maintaining the first conductive layer in the logic region comprises:
forming a patterned masking layer over the first conductive layer, wherein the patterned masking layer protects the first conductive layer in the logic region while forming the select gate.
9. The method of claim 1 , wherein the step of removing the second conductive layer and the charge storage layer from the logic region while maintaining the second conductive layer and the charge storage layer in the NVM region comprises:
forming a second patterned masking layer over the second conductive layer, wherein the second patterned masking layer exposes the second conductive layer in the logic region and protects the second conductive layer in the NVM region.
10. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a gate dielectric layer over the substrate in the NVM region and the logic region;
forming a first metal layer over the gate dielectric layer in the NVM region and the logic region;
patterning the first metal layer in the NVM region to form a select gate while maintaining the first metal layer in the logic region;
forming a charge storage layer over the select gate in the NVM region and the first metal layer in the logic region, wherein the charge storage layer comprises a high-k dielectric material;
forming a second metal layer over the charge storage layer in the NVM region and the logic region;
removing the second metal layer and the charge storage layer from the logic region but not from the NVM region;
patterning the first metal layer in the logic region to form a first logic gate; and
after the patterning the first metal layer in the logic region to form the first logic gate, patterning the second metal layer and the charge storage layer in the NVM region to form a control gate which overlaps a first sidewall of the select gate.
11. The method of claim 10 , wherein after the patterning the first metal layer in the logic region to form the first logic gate and prior to the patterning the second metal layer in the NVM region to form the control gate, the method further comprises:
forming a second gate dielectric layer over the second metal layer in the NVM region and the first logic gate in the logic region;
forming a third metal layer over the second gate dielectric layer in the NVM region and the logic region; and
patterning the third metal layer to remove the third conductive layer and the second gate dielectric layer from the NVM region and to form a second logic gate in the logic region, wherein the first logic gate corresponds to a first transistor having a first conductivity type and the second logic gate corresponds to a second transistor having a second conductivity type, opposite from the first conductivity type.
12. The method of claim 11 , wherein the first conductivity type is further characterized as n-type and the second conductivity type is further characterized as p-type.
13. The method of claim 11 , further comprising:
forming source/drain regions in the substrate adjacent a second sidewall of the select gate and adjacent a sidewall of the control gate;
forming source/drain regions in the substrate adjacent sidewalls of the first logic gate; and
forming source/drain regions in the substrate adjacent sidewalls of the second logic gate.
14. The method of claim 10 , further comprising:
forming source/drain regions in the substrate adjacent a second sidewall of the select gate and adjacent a sidewall of the control gate; and
forming source/drain regions in the substrate adjacent sidewalls of the first logic gate.
15. The method of claim 10 , wherein the step forming the gate dielectric layer comprises forming a high-k dielectric layer.
16. The method of claim 10 , wherein the step of forming the charge storage layer is further characterized in that the charge storage layer comprises a layer of metal nanocrystals surrounded by the high-k dielectric material.
17. The method of claim 10 , wherein the step of patterning the first metal layer in the NVM region to form the select gate while maintaining the first metal layer in the logic region comprises:
forming a first patterned masking layer over the first metal layer, wherein the first patterned masking layer protects the first metal layer in the logic region while forming the select gate.
18. The method of claim 17 , wherein the step of removing the second metal layer and the charge storage layer from the logic region but not from the NVM region comprises:
forming a second patterned masking layer over the second metal layer, wherein the second patterned masking layer exposes the second metal layer in the logic region and protects the second metal layer in the NVM region.
19. A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:
forming a first high-k dielectric layer over the substrate in the NVM region and the logic region;
forming a first metal layer over the first high-k dielectric layer in the NVM region and the logic region;
patterning the first metal layer in the NVM region to form a select gate while maintaining the first metal layer in the logic region;
forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region, wherein forming the charge storage layer comprises:
forming a bottom high-k dielectric layer over the select gate in the NVM region and the first metal layer in the logic region;
forming a plurality of metal nanocrystals over the bottom high-k dielectric layer in the NVM region and the logic region; and
forming a top high-k dielectric layer over the plurality of metal nanocrystals in the NVM region and the logic region;
forming a second metal layer over the charge storage layer in the NVM region and the logic region;
removing the second metal layer and the charge storage layer from the logic region but not from the NVM region;
patterning the first metal layer in the logic region to form a first logic gate;
forming a second high-k dielectric layer over the second metal layer in the NVM region and the first logic gate in the logic region;
forming a third metal layer over the second high-k dielectric layer in the NVM region and the logic region;
patterning the third metal layer to remove the third metal layer and the second high-k dielectric layer from the NVM region and to form a second logic gate in the logic region; and
after forming the first logic gate and the second logic gate, patterning the second metal layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.
20. The method of claim 19 , further comprising:
forming an N-channel logic transistor using the first logic gate; and
forming a P-channel logic transistor using the second logic gate.