Microcontroller including alternative links between peripherals for resource sharing
View Patent ↗A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.
1. A system comprising:
one or more master modules;
a data processing module; and
a system bus that is configured to perform operations comprising:
receiving an instruction from a master module for a transfer of data to a destination;
determining whether additional processing is associated with the transfer; and
based on a determination that additional processing is associated with the transfer, redirecting the transfer to the data processing module by setting an extra address bit in the system bus.
2. The system of claim 1 , wherein the system bus is configurable through a software user interface.
3. The system of claim 1 , wherein redirecting the transfer is based on decoding an input pin associated with the data processing module.
4. The system of claim 1 , wherein redirecting the transfer is based on decoding a transfer address.
5. The system of claim 1 , wherein redirecting the transfer is based on a determination of which master module initiated the data transfer.
6. The system of claim 1 , further comprising one or more peripheral modules, wherein redirecting the transfer is based on determining which of the one or more peripheral modules is a destination for the data transfer.
7. The system of claim 1 , comprising a microcontroller circuit.
8. The system of claim 1 , wherein the data processing module includes instructions for performing encryption and decryption operations.
9. The system of claim 1 , wherein the data processing module comprises a peripheral module including a master interface and a slave interface.
10. The system of claim 1 , wherein one or more additional peripheral modules are configured to ignore a transfer when the extra address bit is set.
11. The system of claim 8 , wherein performing encryption and decryption operations comprises instructions for executing Advanced Encryption Standard (AES) algorithm.
12. A method for resource sharing in a microcontroller circuit, the method comprising:
receiving an instruction on a system bus from a master module for a transfer of data to a destination;
determining whether additional processing is associated with the transfer; and
based on determining that additional processing is associated with the transfer, redirecting the transfer to a data processing module by setting an extra address bit in the system bus.
13. The method of claim 12 , further comprising:
determining, by a data processing module, that the extra address bit is set in the system bus;
based on determining that the extra address bit is set, performing a transfer for the data;
performing additional processing on the data by the data processing module;
placing the additionally processed data on the system bus; and
receiving the additionally processed data by the destination.
14. The method of claim 12 , wherein one or more additional peripheral modules are configured to ignore a transfer when the extra address bit is set.
15. The method of claim 12 , wherein setting the extra address bit in the system bus is further based on determining which master module of one or more master modules initiated the transfer.
16. The method of claim 12 , wherein setting the extra address bit in the system bus is further based on determining which peripheral module of one or more peripheral modules is a destination for the transfer.
17. The method of claim 12 , wherein the transfer includes at least one of a read transfer and a write transfer.
18. The method of claim 12 , wherein the destination includes at least one of a master module and a peripheral module.
19. The method of claim 13 , wherein the data processing module comprises a peripheral module including a master interface and a slave interface.
20. The method of claim 13 , wherein performing additional processing on the data comprises:
performing at least one of encryption and decryption operations on the data.
21. The method of claim 19 , wherein the data processing module is configured to listen on the system bus for transfer instructions.
22. The method of claim 20 , wherein performing at least one of encryption and decryption operations comprises:
performing instructions for executing Advanced Encryption Standard (AES) algorithm.
23. A device comprising:
a system bus;
one or more master modules; and
a data processing module including a master interface and a slave interface, wherein the master and slave interfaces are coupled to the system bus, the system bus configured to:
receive an instruction from a master module for a transfer of data to a destination; and
based on a determination that additional processing is associated with the transfer, redirect the transfer to the data processing module by setting an extra address bit in the system bus.
24. The device of claim 23 , comprising a microcontroller.