IP Library Granted Patent US 8,466,054
Granted Patent B2
US 8,466,054 · App. 13/311,454 · Granted Jun 18, 2013

Thermal conduction paths for semiconductor structures

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Quick Facts
Patent No.
US 8,466,054
App. No.
13/311,454
Granted
Jun 18, 2013
Kind
B2
Abstract

A thermal path is formed in a layer transferred semiconductor structure. The layer transferred semiconductor structure has a semiconductor wafer and a handle wafer bonded to a top side of the semiconductor wafer. The semiconductor wafer has an active device layer formed therein. The thermal path is in contact with the active device layer within the semiconductor wafer. In some embodiments, the thermal path extends from the active device layer to a substrate layer of the handle wafer. In some embodiments, the thermal path extends from the active device layer to a back side external thermal contact below the active device layer.

Claims (39)

1. A method comprising:

forming an active device layer in a semiconductor wafer;

bonding a handle wafer to a top side of the semiconductor wafer; and

forming a thermal path in the semiconductor wafer, the thermal path being in contact with the active device layer.

2. The method of claim 1 , further comprising:

forming the thermal path at least partway to a substrate layer of the handle wafer.

3. The method of claim 2 , further comprising:

forming a back side external thermal contact on the semiconductor wafer; and forming a second thermal path from the back side external thermal contact at least partway to the substrate layer of the handle wafer.

4. The method of claim 2 , further comprising:

forming a back side external thermal contact on the semiconductor wafer; and forming the thermal path in contact with the back side external thermal contact.

5. The method of claim 1 , further comprising:

forming a back side external thermal contact on the semiconductor wafer; and forming the thermal path to the back side external thermal contact.

6. The method of claim 1 , further comprising:

forming the thermal path before the bonding of the handle wafer to the semiconductor wafer.

7. The method of claim 1 , further comprising:

forming the thermal path after the bonding of the handle wafer to the semiconductor wafer.

8. The method of claim 7 , wherein:

the handle wafer comprises a substrate layer; and

the thermal path extends from the active device layer to the substrate layer.

9. The method of claim 5 , wherein:

the back side external thermal contact covers a substantial portion of a back side of the semiconductor wafer.

10. The method of claim 7 , further comprising:

etching a back side of the semiconductor wafer to form an excavation area for the thermal path.

11. The method of claim 5 , wherein:

a single deposition step forms both the back side external thermal contact and a portion of the thermal path, the portion of the thermal path being in contact with the active device layer.

12. The method of claim 7 , further comprising:

forming a back side external thermal contact on the semiconductor wafer; and

forming the thermal path to the back side external thermal contact.

13. The method of claim 12 , wherein:

the thermal path is formed of material that is not electrically conductive.

14. The method of claim 12 , wherein:

the back side external thermal contact covers a substantial portion of a back side of the semiconductor wafer.

15. The method of claim 14 , wherein:

the handle wafer comprises a substrate layer; and

the thermal path extends from the active device layer to the substrate layer.

16. The method of claim 1 , further comprising:

forming a back side external thermal contact on the semiconductor wafer; and

forming a second thermal path extending from the back side external thermal contact to a substrate layer of the handle wafer;

wherein the back side external thermal contact is a part of the thermal path, the active device layer is in an active layer of the semiconductor wafer, and the thermal path terminates in the active layer.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: QUALCOMM SWITCH CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 038794/0663 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUS PATENT NUMBER 9029901 TO THE CORRECT PATENT NO. 9029201 AS PREVIOUSLY RECORDED ON REEL 036812 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST AGAINST ALL PATENTS SET FORTH HEREIN. Recorded Oct 20, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036907/0785 →
CHANGE OF NAME Recorded Oct 16, 2015
From: SILANNA SEMICONDUCTOR U.S.A., INC.
To: QUALCOMM SWITCH CORP.
Reel/Frame 036877/0140 →
TERMINATION AND RELEASE OF GRANT OF SECURITY INTEREST (PATENTS) Recorded Oct 7, 2015
From: HSBC BANK AUSTRALIA LIMITED ABN 48 006 434 162
To: SILANNA SEMICONDUCTOR U.S.A., INC. (FORMERLY KNOWN AS IO SEMICONDUCTOR)
Reel/Frame 036812/0429 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 027337 FRAME: 0346. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 20, 2015
From: STUBER, MICHAEL A.; BRINDLE, CHRIS; MOLIN, STUART B.
To: IO SEMICONDUCTOR INCORPORATED
Reel/Frame 036139/0014 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033134 FRAME: 0338. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 15, 2015
From: IO SEMICONDUCTOR INCORPORATED
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 036109/0237 →
CHANGE OF NAME Recorded Jun 11, 2014
From: IO SEMICONDUCTOR, INC.
To: SILANNA SEMICONDUCTOR U.S.A., INC.
Reel/Frame 033134/0338 →
SECURITY AGREEMENT Recorded Feb 4, 2013
From: IO SEMICONDUCTOR INCORPORATED
To: HSBC BANK AUSTRALIA LIMITED
Reel/Frame 029751/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2011
From: STUBER, MICHAEL A; BRINDLE, CHRIS; MOLIN, STUART B
To: IO SEMICONDUCTOR, INC.
Reel/Frame 027337/0346 →