Electrical test structure for devices employing high-k dielectrics or metal gates

1. A test structure, comprising:

an isolation region formed in a semiconducting substrate;

a first line formed on and in contact with, and extending over an upper surface of, said isolation region;

a first active region defined by said isolation region in said semiconducting substrate; and

a first extension formed on and in contact with said upper surface of said isolation region, said first extension extending laterally over said upper surface of said isolation region from a first side of said first line, wherein said first extension is positioned proximate said first active region and wherein said first line and said first extension are comprised of at least one of a high-k layer of insulating material or a metal layer.

2. The test structure of claim 1 , wherein said first line has a first width and said first extension has a second width, wherein said second width is less than said first width.

3. The test structure of claim 1 , further comprising a second active region defined by said isolation region in said semiconducting substrate, wherein at least a portion of said first extension extends between said first and second active regions.

4. The test structure of claim 1 , further comprising a second extension formed on and in contact with said upper surface of said isolation region and extending laterally over said upper surface of said isolation region from a second side of said first line, said second side of said first line being opposite said first side of said first line, wherein said second extension is comprised of at least one of said high-k layer of insulating material or said metal layer.

5. The test structure of claim 4 , further comprising a second active region defined by said isolation region in said semiconducting substrate, wherein said second extension is positioned proximate said second active region.

6. The test structure of claim 4 , wherein said first extension and said second extension extend the same distance laterally away from said first line.

7. The test structure of claim 4 , wherein said first extension and said second extension extend different distances laterally away from said first line.

8. The test structure of claim 4 , wherein said first extension and said second extension have different widths.

9. The test structure of claim 1 , wherein said first line and said first extension are comprised of said high-k layer of insulating material and said metal layer, said metal layer being positioned above said high-k layer of insulating material, and a layer of material positioned above said metal layer, wherein an electrical conductivity of said layer of material is less than an electrical conductivity of said metal layer.

10. The test structure of claim 9 , wherein said layer of material is a non-silicided silicon-containing material.

11. The test structure of claim 10 , wherein said non-silicided silicon-containing material is one of a non-silicided polysilicon or a non-silicided amorphous silicon.

12. A test structure, comprising:

an isolation region formed in a semiconducting substrate;

a first line formed on and in contact with, and extending over an upper surface of, said isolation region;

a first and a second active region defined by said isolation region in said semiconducting substrate proximate a first side of said first line;

a first extension formed on and in contact with said upper surface of said isolation region, said first extension extending laterally over said upper surface of said isolation region from said first side of said first line, wherein at least a portion of said first extension extends between said first and second active regions;

a third and a fourth active region defined by said isolation region in said semiconducting substrate proximate a second side of said first line, said second side of said first line being opposite said first side of said first line; and

a second extension formed on and in contact with said upper surface of said isolation region and extending laterally over said upper surface of said isolation region from said second side of said first line, wherein at least a portion of said second extension extends between said third and fourth active regions, wherein said first line and said first and second extensions are comprised of at least one of a high-k layer of insulating material or a metal layer.

13. The test structure of claim 12 , wherein said first line has a first width and said first extension and said second extension have a second common width, wherein said second common width is less than said first width.

14. The test structure of claim 12 , wherein said first extension and said second extension extend the same distance laterally away from said first line.

15. The test structure of claim 12 , wherein said first extension and said second extension extend different distances laterally away from said first line.

16. The test structure of claim 12 , wherein said first extension and said second extension have different widths.

17. The test structure of claim 12 , wherein said first and second extensions are positioned opposite one another.

18. The test structure of claim 12 , wherein said first line and said first and second extensions are comprised of said high-k layer of insulating material and said metal layer, said metal layer being positioned above said high-k layer of insulating material, and a layer of material positioned above said metal layer, wherein an electrical conductivity of said layer of material is less than an electrical conductivity of said metal layer.

19. The test structure of claim 18 , wherein said layer of material is a non-silicided silicon-containing material.

20. The test structure of claim 19 , wherein said non-silicided silicon-containing material is one of a non-silicided polysilicon or a non-silicided amorphous silicon.

21. A test structure comprising:

an isolation region formed in a semiconducting substrate;

a first line formed on and in contact with, and extending over an upper surface of, said isolation material;

a first active region, a second active region, a third active region and a fourth active region defined by said isolation region in said semiconducting substrate, said first and second active regions being formed proximate a first side of said first line while said third and fourth active regions are formed proximate a second side of said first line, said second side of said first line being opposite said first side of said first line;

a first extension formed on and in contact with said upper surface of said isolation region, said first extension extending laterally over said upper surface of said isolation region from said first side of said first line, wherein at least a portion of said first extension extends between said first and second active regions; and

a second extension formed on and in contact with said upper surface of said isolation region and extending laterally over said upper surface of said isolation region from said second side of said first line, said second extension being opposite said first extension, wherein at least a portion of said second extension extends between said third and fourth active regions, and wherein said first line and said first and second extensions are comprised of a high-k layer of insulating material, a metal layer positioned above said high-k layer of insulating material, and a layer of material positioned above said metal layer, wherein an electrical conductivity of said layer of material is less than an electrical conductivity of said metal layer.