Trap rich layer for semiconductor devices
View Patent ↗An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.
1. A method comprising:
forming an active layer for an integrated circuit chip, the active layer including an active device layer and a metal interconnect layer; and
forming a trap rich layer above the active layer, wherein the trap rich layer remains in a final structure for the integrated circuit chip.
2. The method of claim 1 , further comprising:
forming the trap rich layer by one of implantation damage, radiation damage and mechanical damage.
3. The method of claim 1 , further comprising:
forming the trap rich layer after the forming of the active layer.
4. The method of claim 1 , further comprising:
forming the active layer in a semiconductor wafer;
forming the trap rich layer in a handle wafer; and
bonding the handle wafer to the semiconductor wafer.
5. The method of claim 4 , further comprising:
forming a bonding layer on the handle wafer; and
forming the trap rich layer after the forming of the bonding layer.
6. The method of claim 4 , further comprising:
bonding the handle wafer to a top side of the semiconductor wafer; and
removing at least a portion of a semiconductor substrate on a back side of the semiconductor wafer.
7. The original method of claim 4 , further comprising:
forming the trap rich layer in the handle wafer before the bonding of the handle wafer to the semiconductor wafer.
8. The method of claim 4 , further comprising:
forming a second active layer in the handle wafer;
forming the trap rich layer in the handle wafer below the second active layer; and
bonding the handle wafer to a top side of the semiconductor wafer.
9. The method of claim 8 , wherein the forming of the trap rich layer in the handle wafer further comprises:
bonding a second handle wafer to a top side of the handle wafer;
removing at least a portion of a substrate on a back side of the handle wafer;
forming the trap rich layer in a third handle wafer; and
bonding the third handle wafer to the back side of the handle wafer.
10. The method of claim 4 , further comprising:
irradiating the handle wafer to form the trap rich layer by radiation damage.
11. The method of claim 10 , further comprising:
forming a bonding layer on the handle wafer; and
irradiating the handle wafer to form the trap rich layer after the forming of the bonding layer.
12. The method of claim 10 , further comprising:
irradiating the handle wafer to form the trap rich layer in a batch process in which multiple wafers are irradiated together.
13. The method of claim 4 , further comprising:
bonding the handle wafer to the semiconductor wafer after the forming of the active layer.
14. The method of claim 1 , further comprising:
forming the active layer and the trap rich layer in a semiconductor wafer; and bonding a handle wafer to the semiconductor wafer above the trap rich layer.
15. An integrated circuit chip comprising:
an active layer including an active device layer and a metal interconnect layer; and
a trap rich layer located above the active layer; wherein the trap rich layer remains in a final structure of the integrated circuit chip.
16. An integrated circuit chip of claim 15 , wherein:
the trap rich layer is formed by one of implantation damage, radiation damage and mechanical damage.
17. The integrated circuit chip of claim 15 , further comprising:
the trap rich layer is added to the integrated circuit chip after formation of the active layer.
18. The integrated circuit chip of claim 15 , further comprising:
a semiconductor wafer comprising the active layer; and
a handle wafer bonded to the semiconductor wafer, the handle wafer comprising the trap rich layer.
19. The integrated circuit chip of claim 18 , wherein:
the handle wafer further comprises a bonding layer; and
the trap rich layer is formed after formation of the bonding layer.
20. The integrated circuit chip of claim 18 , wherein:
the handle wafer is bonded to a top side of the semiconductor wafer; and
at least a portion of a semiconductor substrate has been removed from a back side of the semiconductor wafer.
21. The integrated circuit chip of claim 18 , wherein:
the trap rich layer is formed in the handle wafer before the handle wafer is bonded to the semiconductor wafer.
22. The integrated circuit chip of claim 18 , wherein:
the handle wafer further comprises a second active layer;
the trap rich layer is below the second active layer in the handle wafer; and
the handle wafer is bonded to a top side of the semiconductor wafer.
23. The integrated circuit chip of claim 22 , wherein:
the trap rich layer is formed in a second handle wafer that is bonded to a back side of the handle wafer.
24. The integrated circuit chip of claim 18 , wherein:
the trap rich layer is formed in the handle wafer by radiation damage.
25. The integrated circuit chip of claim 24 , wherein:
the handle wafer further comprises a bonding layer; and
the trap rich layer is formed by radiation damage after the forming of the bonding layer.
26. The integrated circuit chip of claim 24 , wherein:
the handle wafer is irradiated to form the trap rich layer in a batch process in which multiple wafers are irradiated together.
27. The integrated circuit chip of claim 18 , wherein:
the handle wafer is bonded to the semiconductor wafer after formation of the active layer.
28. The integrated circuit chip of claim 15 , further comprising:
a semiconductor wafer comprising the active layer and the trap rich layer; and
a handle wafer bonded to the semiconductor wafer above the trap rich layer.
29. An integrated circuit chip comprising:
a semiconductor wafer having an active layer, the active layer including an active device layer and a metal interconnected layer; and
a handle wafer bonded to a top side of the semiconductor wafer after formation of the active layer, the handle wafer having a trap rich layer formed before the handle wafer is bonded to the semiconductor wafer; wherein the trap rich layer remains in a final structure of the integrated circuit chip.
30. The integrated circuit chip of claim 29 , wherein:
the aforementioned active layer is a first active layer;
the handle wafer further has a second active layer, the second active layer including a second active device layer and a second metal interconnect layer; and
the trap rich layer is between the first and second active layers.