Using a single terminal for a power enable output signal and detecting an over-current condition
View Patent ↗A power controller for a peripheral bus interface. A peripheral bus power controller includes a first terminal, a second terminal coupled to receive an power enable input signal from a host controller, and a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller. The peripheral bus power controller further includes an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal and a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.
1. A peripheral bus power controller comprising:
a first terminal of the peripheral bus power controller;
a second terminal coupled to receive an power enable input signal from a host controller;
a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller;
an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal; and
a first buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.
2. The power controller as recited in claim 1 , wherein the power controller is implemented in an integrated circuit package having a plurality of pins, wherein the first terminal comprises one of the plurality of pins.
3. The power controller as recited in claim 1 , further comprising a filter coupled to an output of the first buffer.
4. The power controller as recited in claim 1 , wherein the power enable output signal is driven at a first logic level onto the first terminal, and wherein detecting an over-current condition includes detecting a second logic level on the first terminal.
5. The power controller as recited in claim 4 , wherein the first logic level is a logic high level, and wherein the second logic level is a logic low level.
6. A computer system comprising:
a peripheral bus host controller; and
at least one peripheral port coupled to a peripheral bus and the host controller, wherein the at least one peripheral port includes a peripheral bus power controller comprising:
a first terminal of the peripheral bus power controller;
a second terminal coupled to receive a power enable input signal from the host controller;
a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller;
a first circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal; and
second circuit configured to provide an over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.
7. The computer system as recited in claim 6 , wherein the peripheral bus power controller is implemented in an integrated circuit package having a plurality of pins, and wherein the first terminal is comprises one of the plurality of pins.
8. The computer system as recited in claim 6 , wherein the peripheral port further includes a power switch coupled to the first terminal of the peripheral bus power controller, wherein the power switch is configured to provide power to a peripheral device coupled to the peripheral bus responsive to receiving the power enable output signal from the peripheral bus power controller.
9. The computer system as recited in claim 6 , wherein the peripheral port further includes a resettable fuse coupled between a first voltage node and a second voltage node, and a diode having an anode coupled to the first terminal and a cathode coupled to the second voltage node.
10. The computer system as recited in claim 9 , wherein the resettable fuse is configured to open responsive to an over current condition.
11. The computer system as recited in claim 6 , further comprising a peripheral device coupled to the peripheral bus, wherein the peripheral device is coupled to receive power through the second voltage node.
12. The computer system as recited in claim 11 , wherein the peripheral bus includes a true data signal path and a complementary signal data path.
13. The computer system as recited in claim 6 , wherein the power enable output signal is driven at a first logic level onto the first terminal, and wherein detecting an over-current condition includes detecting a second logic level on the first terminal.
14. The computer system as recited in claim 13 , wherein the first logic level is a logic high level, and wherein the second logic level is a logic low level.
15. The computer system as recited in claim 6 , wherein the peripheral bus is a Universal Serial Bus.