IP Library › Granted Patent US 8,969,188
Granted Patent B2
US 8,969,188 · App. 13/326,700 · Granted Mar 3, 2015

Methods of fabricating semiconductor devices

Inventors: Ki-chul Kim (Gyeonggi-do, KR); Jong-cheol Lee (Seoul, KR); Heung-ahn Kwon (Gyeonggi-do, KR); Hyun-wook Lee (Seoul, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L21/28273H01L21/28282H01L27/10852H01L28/65H01L29/42324H01L29/4234H01L29/51H01L29/513
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Quick Facts
Patent No.
US 8,969,188
App. No.
13/326,700
Granted
Mar 3, 2015
Kind
B2
Abstract

Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

Claims (33)

1. A method of manufacturing a semiconductor device, the method comprising:

forming a multi-layer of dielectric layers on a semiconductor substrate, the multi-layer of dielectric layers including at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer; and

after forming the multi-layer of dielectric layers, forming an upper electrode layer on the multi-layer of dielectric layers,

wherein the multi-layer of dielectric layers is crystallized at a temperature at which the upper electrode layer is formed.

2. The method according to claim 1 , wherein forming the multi-layer of dielectric layers comprises:

forming a metal oxide layer on the semiconductor substrate; and

forming a multi-layer of silicate layers on the metal oxide layer, the multi-layer of silicate layers including metal atoms and silicon atoms.

3. The method according to claim 2 , wherein forming the multi-layer of silicate layers comprises:

forming a first metallic silicate layer having a first silicon concentration; and

forming a second metallic silicate layer having a second silicon concentration that is higher than the first silicon concentration.

4. The method according to claim 3 , wherein the first metallic silicate layer and the second metallic silicate layer each comprise a hafnium-zirconium silicate.

5. The method according to claim 3 , wherein forming the multi-layer of silicate layers comprises forming at least two first metallic silicate layers, and

wherein the second metallic silicate layer is disposed between the at least two first metallic silicate layers.

6. The method according to claim 3 , wherein forming the multi-layer of silicate layers comprises forming at least two second metallic silicate layers,

wherein the first metallic silicate layer is disposed between the at least two second metallic silicate layers.

7. The method according to claim 3 , wherein forming the multi-layer of silicate layers comprises forming the first metallic silicate layer to have a first thickness and forming the second metallic silicate layer to have a second thickness that is smaller than the first thickness.

8. The method according to claim 3 , wherein forming the multi-layer of silicate layers comprises forming the first metallic silicate layer to have a first thickness and forming the second metallic silicate layer to have a second thickness, and

wherein forming the metal oxide layer comprises forming the metal oxide layer to have a third thickness that is smaller than the first thickness, the second thickness and/or a sum of the first thickness and the second thickness.

9. The method according to claim 2 , wherein in forming the upper electrode layer, the multi-layer of silicate layers is crystallized to have a cubic system, tetragonal system, or orthorhombic system crystalline structure.

10. The method according to claim 2 , wherein forming the upper electrode layer comprises applying a process temperature that forms the upper electrode and that crystallizes the multi-layer of silicate layers to have a cubic system, tetragonal system, or orthorhombic system crystalline structure.

11. The method according to claim 10 , wherein the process temperature crystallizes the metal oxide layer.

12. The method according to claim 2 , wherein the metal oxide layer comprises a zirconium oxide, a hafnium oxide, and/or a hafnium-zirconium oxide.

13. The method according to claim 2 , wherein the multi-layer of silicate layers comprises a hafnium silicate, a zirconium silicate, and/or a hafnium-zirconium silicate.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a metal oxide layer on a semiconductor substrate;

forming a first hafnium-zirconium silicate layer on the metal oxide layer;

forming a second hafnium-zirconium silicate layer having a higher silicon concentration than that of the first hafnium-zirconium silicate layer, on the first hafnium-zirconium silicate layer; and

forming an upper electrode layer on the second hafnium-zirconium silicate layer,

wherein the hafnium-zirconium oxide layer, the first hafnium-zirconium silicate layer, and the second hafnium-zirconium silicate layer are crystallized at a process temperature at which the upper electrode layer is formed.

15. The method according to claim 14 , wherein the metal oxide layer includes a hafnium-zirconium oxide layer.

16. The method according to claim 14 , wherein the process temperature is in a temperature range of about 400° C. to about 750° C.

17. The method according to claim 1 , wherein the temperature at which the upper electrode layer is formed is in a temperature range of about 400° C. to about 750° C.

18. The method according to claim 1 , wherein the multi-layer of silicate layers is crystallized while the upper electrode layer is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2011
From: KIM, KI-CHUL; LEE, JONG-CHEOL; KWON, HEUNG-AHN; LEE, HYUN-WOOK
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 027390/0761 →
Priority Claims (1)
KR 10-2010-0129309 · Dec 16, 2010 · national
Continuity (3)
Continuation In Part 12238822 · Sep 26, 2008
Continuation In Part 13019636 · Feb 2, 2011
Related Publication 20120088360A1 · Apr 12, 2012