Termination control circuit and semiconductor device including the same

1. A semiconductor device comprising:

a termination control unit configured to generate a termination enable signal and termination resistance information in response to termination activation information and, dynamic activation information, normal resistance information, and dynamic resistance information, wherein the termination control unit activates the termination enable signal when a delay lock loop is inactivated; and

a termination unit configured to be controlled in response to the termination enable signal and terminate an interface pad by using a resistance value determined by the termination resistance information.

2. The semiconductor device of claim 1 , wherein the termination control unit is configured to activate the termination enable signal when one of a termination operation and a dynamic termination operation is performed.

3. The semiconductor device of claim 2 , wherein the termination control unit is configured to transmit the normal resistance information as the termination resistance information when the termination operation is performed and transmit the dynamic resistance information as the termination resistance information when the dynamic termination operation is performed.

4. The semiconductor device of claim 1 , wherein the termination control unit is configured to inactivate the termination enable signal in response to an output enable signal activated when a read command is applied.

5. The semiconductor device of claim 4 , wherein the termination activation information includes a termination signal and a termination disable signal and the dynamic activation information includes a dynamic termination signal and a dynamic termination disable signal.

6. The semiconductor device of claim 5 , wherein the termination control unit includes:

an enable signal generation unit configured to generate the termination enable signal in response to the termination activation information, the dynamic activation information, and a delay lock disable signal indicating whether the delay lock loop is inactivated; and

a resistance information generation unit configured to transmit one of the normal resistance information and the dynamic resistance information as the termination resistance information, in response to the termination signal, the dynamic termination signal, and the delay lock disable signal.

7. The semiconductor device of claim 6 , wherein the enable signal generation unit is configured to activate the termination enable signal when the delay lock disable signal is activated and one of the termination disable signal and the dynamic termination disable signal is inactivated, when the termination signal is activated and the termination disable signal is inactivated, or when the dynamic termination signal is activated and the dynamic termination disable signal are inactivated, and inactivate the termination enable signal when the output enable signal is activated.

8. The semiconductor device of claim 6 , wherein the resistance information generation unit is configured to transmit the normal resistance information as the termination resistance information when the termination signal is activated and the dynamic termination signal is inactivated and transmit the dynamic resistance information as the termination resistance information when the termination signal and the dynamic termination signal are activated, and transmit the dynamic resistance information as the termination resistance information when the delay lock disable signal is activated.

9. The semiconductor device of claim 1 , wherein the semiconductor device is a memory device and the interface pad is a data input/output pad.

10. The semiconductor device of claim 9 , wherein the termination disable signal, the dynamic termination disable signal, the normal resistance information, and the dynamic resistance information are determined by a mode register setting.

11. The semiconductor device of claim 1 , wherein the termination signal is a signal applied from the outside of the semiconductor device and the dynamic termination signal is activated in a write operation period of the semiconductor device when the termination signal is activated.

12. A termination control circuit comprising:

an enable signal generation unit configured to generate termination enable signal in response to a termination signal, a termination disable signal, a dynamic termination signal, a dynamic termination disable signal, and a delay lock disable signal indicating whether a delay lock loop is inactivated; and

a resistance information generation unit configured to transmit one of the normal resistance information and the dynamic resistance information as a termination resistance information in response to the termination signal, the dynamic termination signal, and the delay lock disable signal.

13. The termination control circuit of claim 12 , wherein the enable signal generation unit is configured to activate the termination enable signal when the delay lock disable signal is activated and the termination disable signal or the dynamic termination disable signal is inactivated, when the termination signal is activated and the termination disable signal is inactivated, or when the dynamic termination signal is activated and the dynamic termination disable signal are inactivated, and inactivate the termination enable signal when an output enable signal is activated.

14. The termination control circuit of claim 12 , wherein the resistance information generation unit is configured to transmit the normal resistance information as the termination resistance information when the termination signal is activated and the dynamic termination signal is inactivated and transmits the dynamic resistance information as the termination resistance information when the termination signal and the dynamic termination signal are activated, and transmit the dynamic resistance information as the termination resistance information when the delay lock disable signal is activated.

15. The termination control circuit of claim 12 , wherein the termination disable signal, the dynamic termination disable signal, the normal resistance information, and the dynamic resistance information are determined by a mode register setting.

16. The termination control circuit of claim 12 , wherein the termination signal includes a signal activated at the time of the termination operation and the dynamic termination signal includes a signal activated in a write operation period of the semiconductor device when the termination signal is activated.

17. The termination control circuit of claim 12 , wherein the enable signal generation unit is configured to activate the termination enable signal when the delay lock disable signal is activated and inactivate the termination enable signal when an output enable signal is activated.

18. The termination control circuit of claim 17 , wherein the enable signal generation unit is configured to activate the termination enable signal for performing a dynamic termination when an output enable signal is inactivated and the delay lock disable signal is in an active state.