Semiconductor device and testing method thereof
View Patent ↗A semiconductor device includes a plurality of cell blocks activated in response to a plurality of selection signals, respectively, a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and activate at least two of the pre-selection signals by decoding addresses in a multi-test mode, a selection signal controller configured to selectively activate the plurality of selection signals in response to the plurality pre-selection signals and control active periods of the activated selection signals so as not to overlap, and a decision circuit configured to decide whether or not the cell blocks activated in response to the activated selection signals are repaired in response to stored repair information and the plurality of selection signals.
1. A semiconductor device comprising:
a plurality of cell blocks activated in response to a plurality of selection signals, respectively;
a pre-selection signal generator configured to generate a plurality of pre-selection signals corresponding to the cell blocks, respectively, and simultaneously activate at least two of the pre-selection signals by decoding addresses in a multi-test mode;
a selection signal controller configured to selectively activate the plurality of selection signals by controlling active periods of the simultaneously activated pre-selection signals so as not to overlap in response to a sequence control signal and a driving control signal; and
a decision circuit configured to decide whether or not the activated cell blocks are repaired in response to stored repair information and the activated selection signals.
2. The semiconductor device of claim 1 , wherein the decision circuit comprises a plurality of fuses corresponding to the selection signals, respectively, and the decision unit is configured to activate a first signal in response to cut states of fuses corresponding to the activated selection signals.
3. The semiconductor device of claim 2 , wherein one of the fuses corresponding to a repaired cell block of the plurality of cell blocks is cut and the other fuses are not cut.
4. The semiconductor device of claim 1 , wherein the decision circuit comprises:
a plurality of fuses connected in parallel to a first node;
a plurality of switches that each have one node connected to a second node and another node connected to a corresponding one of the plurality of fuses and are turned on/off in response to the plurality of selection signals, respectively; and
an output unit configured to activate a first signal a selected one of the switches is turned on in response to the activated selection signals and the respective fuse connected in series to the switch is cut and inactivate the first signal when the fuse is not cut.
5. The semiconductor device of claim 1 , wherein the decision circuit comprises:
a plurality of switches connected in parallel to a first node, wherein each of the switches is turned on/off in response to a corresponding one of the plurality of selection signals;
a plurality of fuses that each have one node connected to a second node and another node connected to one of the switches; and
an output unit configured to activate a first signal when a selected one of the switches is turned on in response to the activated selection signals and the respective fuse connected in series to the switch is cut and inactivate the first signal when the fuse is not cut.
6. The semiconductor device of claim 4 , wherein the output unit comprises:
a pre-charger configured to pre-charge a voltage at the first node at a first level in response to a driving control signal; and
a driver configured to maintain the voltage at the first node at the first level and activate the first signal when the fuse connected in series to the selected switch is cut and change the voltage at the first node from the first level to a second level when the fuse is not cut.
7. The semiconductor device of claim 6 , wherein
the second node is connected to a ground node, and the first and second levels are high and low levels, respectively; and
the driver is configured to maintain the voltage at the first node at a high level and activate the hit signal when the fuse connected in series the selected switch is cut and drop the voltage at the first node from the high level to a low level when the fuse is not cut.
8. The semiconductor device of claim 1 , wherein each of the plurality of cell blocks comprises at least one word line.
9. The semiconductor device of claim 1 , wherein the selection signal controller is configured to control the activated selection signals to be sequentially activated and outputted.
10. The semiconductor device of claim 1 , wherein the selection signal controller comprises:
an activation sequence controller configured to control an activation sequence of the activated selection signals in response to at least one sequence control signal; and
a period controller configured to control lengths of activation periods of the activated selection signals, wherein an activation sequence of the activated selection signals is controlled by the activation sequence controller in response to the driving control signal.
11. The semiconductor device of claim 10 , wherein the driving control signal is generated using a read or write command.
12. The semiconductor device of claim 10 , further comprising the driving control signal generator including:
a pulse generator configured to generate a pulse signal in response to a read or write command in the multi-test mode;
a shifter configured to shift the pulse signal and output the shifted pulse signal; and
a processor configured to generate the driving control signal by combining the pulse signal and the shifted pulse signal.
13. A testing method of a semiconductor device having a plurality of cell blocks that are activated in response a plurality of selection signals, respectively, the method comprising:
generating a plurality of pre-selection signals corresponding to the cell blocks, respectively, and simultaneously activating at least two of the pre-selection signals by decoding addresses in a multi-test mode;
selectively activating the selection signals by controlling active periods of the simultaneously activated pre-selection signals so as not to overlap in response to a sequence control signal and a driving control signal; and
deciding whether or not the activated cell blocks are repaired in response to stored repair information stored and the activated selection signals.
14. The method of claim 13 , wherein the selectively activating of the selection signals comprises:
selectively activating the plurality of selection signals in response to the plurality of pre-selection signals;
generating the sequence control signal for controlling an activation sequence of the activated selection signals; and
controlling the activated selection signals to be sequentially activated in response to the sequence control signal.
15. The method of claim 13 , further comprising:
controlling lengths of the activation periods of the activated selection signals in response to the driving control signal after the controlling of active periods of the activated selection signals so as not to overlap.
16. The method of claim 15 , wherein the driving control signal is generated using a read or write command.
17. The method of claim 15 , further comprising:
generating a pulse signal in response to a read or write command in the multi-test mode;
shifting the pulse signal to output the shifted pulse signal; and
generating the driving control signal by combining the pulse signal and the shifted pulse signal.
18. A semiconductor device comprising:
a driving control signal generator configured to generate a driving control signal in response to a read or write command in a test mode;
a pre-selection signal generator configured to generate a plurality of pre-selection signals, and simultaneously activate at least two of the pre-selection signals by decoding addresses in the test mode;
a selection signal controller configured to selectively activate a plurality of selection signals by controlling active periods of the simultaneously activated pre-selection signals so as not to overlap in response to sequence control signal and the driving control signal; and
a decision circuit configured to receive the plurality of selection signals to decide a logic level of a hit signal in response to stored repair information and the driving control signal.
19. The semiconductor device of claim 18 , wherein the driving control signal generator comprises:
a pulse generator configured to generate a pulse signal in response to the read or write command in the test mode;
a shifter configured to shift the pulse signal and output the shifted pulse signal; and
a processor configured to generate the driving control signal by combining the pulse signal and the shifted pulse signal.
20. The semiconductor device of claim 18 , wherein the selection signal controller comprises:
an activation sequence controller configured to control an activation sequence of the activated selection signals in response to at least one sequence control signal; and
a period controller configured to control lengths of activation periods of the activated selection signals, wherein an activation sequence of the activated selection signals is controlled by the activation sequence controller in response to the driving control signal.