Embedded wafer level optical package structure and manufacturing method

1. A method of forming an embedded wafer level optical package comprising:

attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier;

attaching a dam between two light sensitive sensors of the sensor die;

encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer;

debonding the carrier;

grinding a top surface of the encapsulation layer;

forming vias through the encapsulation layer to the sensor die and the LED;

filling the vias with conductive material;

metalizing the top surface of the encapsulation layer;

dielectric coating of the top surface of the encapsulation layer;

dielectric coating of a bottom surface of the encapsulation layer;

patterning the dielectric coating of the bottom surface of the encapsulation layer; and

plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

2. The method of claim 1 further comprising solder balling the plated and patterned dielectric coating of the bottom surface of the encapsulation layer.

3. The method of claim 1 , wherein the dam comprises a mold compound.

4. The method of claim 1 , wherein the dam comprises silicon.

5. The method of claim 1 , wherein attaching the dam comprises attachment using UV light.

6. The method of claim 1 , wherein attaching the dam comprises attachment using a heat curable glue.

7. The method of claim 1 , wherein encapsulating comprises encapsulation using a transparent mold compound.

8. The method of claim 1 , wherein grinding the encapsulation layer comprises grinding to a thickness that exposes the PCB bars.

9. The method of claim 1 , wherein the vias are formed using laser drilling.

10. The method of claim 1 , wherein the vias are formed using laser ablation.

11. The method of claim 1 , wherein metalizing the top surface of the encapsulation layer comprises metalizing with copper lines.

12. The method of claim 1 , wherein metalizing the top surface of the encapsulation layer comprises sputtering, patterning and plating.

13. The method of claim 1 , wherein dielectric coating of the top surface comprises using a transparent dielectric material.

14. The method of claim 1 , wherein patterning the dielectric coating of the bottom surface of the encapsulation layer comprises using a lithography process.

15. The method of claim 1 , wherein plating the patterned dielectric coating of the bottom surface of the encapsulation layer comprises using UBM (Under Bump Metalization) plating.

16. A method of forming an embedded wafer level optical package comprising:

providing a sensor die, PCB bars, an LED, and a dam on the sensor die;

encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer;

grinding the encapsulation layer;

forming vias through the encapsulation layer to the sensor die and the LED;

filling the vias with conductive material;

metalizing a top surface of the encapsulation layer; and

dielectric coating of the top surface of the encapsulation layer.

17. The method of claim 16 further comprising dielectric coating of a bottom surface of the encapsulation layer.

18. The method of claim 17 further comprising patterning the dielectric coating of the bottom surface of the encapsulation layer.

19. The method of claim 18 further comprising plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

20. The method of claim 19 further comprising solder balling the plated and patterned dielectric coating of the bottom surface of the encapsulation layer.

21. A method of forming an embedded wafer level optical package comprising:

providing a sensor die, PCB bars, an LED, and a dam on the sensor die;

transparently encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer;

forming conductive vias through the encapsulation layer to the sensor die and the LED;

metalizing a top surface of the encapsulation layer; and

transparent dielectric coating of the top surface of the encapsulation layer.