Repair method and integrated circuit using the same

1. An integrated circuit comprising:

a memory controller configured to determine whether a memory cell included in a semiconductor memory device is defective or not and extract a fail address having positional information of the defective memory cell, in a test mode; and

a fail address storage unit configured to store the fail address,

wherein the semiconductor memory device comprises:

a fail address register configured to store the fail address;

an internal address generation unit configured to receive a external address and count and generate an internal address;

an address comparison unit configured to compare the fail address with the internal address and generate a repair signal;

an address decoder configured to enable a word line select signal and a bit line select signal of a memory cell corresponding to the test address or enable the word line select signal and the bit line select signal of a memory cell corresponding to the internal address, in response to the test mode enable signal and the repair signal; and

a redundant address decoder configured to enable a redundant word line select signal and a redundant bit line select signal of a redundant cell in response to the repair signal.

2. The integrated circuit of claim 1 , wherein the memory controller outputs the test address which is sequentially counted when the integrated circuit enters the test mode, and outputs input data which is to be written into the memory cell.

3. The integrated circuit of claim 2 , wherein the memory controller outputs the test address as the fail address, when the input data is not identical to output data read from the semiconductor memory device.

4. The integrated circuit of claim 1 , wherein the fail address storage unit comprises a nonvolatile element.

5. The integrated circuit of claim 1 , wherein the memory controller receives the fail address from the fail address storage unit and outputs the fail address and the external address, when the integrated circuit exits from the test mode.

6. The integrated circuit of claim 1 , wherein the memory controller receives the fail address from the fail address storage unit and outputs the fail address.

7. The integrated circuit of claim 1 wherein the test mode enable signal is enabled when the integrated circuit enters the test mode.

8. The integrated circuit of claim 1 , wherein the repair signal is enabled when the fail address is identical to the internal address.

9. The integrated circuit of claim 1 , wherein the address comparison unit comprises:

a first exclusive nor gate configured to compare a first fail address and a first internal address and generate a first comparison signal;

a second exclusive nor gate configured to compare a second fail address and a second internal address and generate a second comparison signal; and

a third exclusive nor gate configured to compare the first comparison signal with the second comparison signal and generate a repair signal.

10. The integrated circuit of claim 1 , wherein the semiconductor memory device further comprises:

a memory cell block comprising a plurality of memory cells which are driven in response to the word line select signal and the bit line select signal; and

a redundant cell block comprising a plurality of redundant cells which are driven in response to the redundant word line select signal and the redundant bit line select signal.

11. The integrated circuit of claim 10 , wherein the memory cell block writes the input data when entering the test mode to perform a write operation, and outputs the input data as the output data when performing a read operation.

12. A repair method of an integrated circuit, comprising:

determining whether a memory cell included in a semiconductor memory device is defective or not and extracting a fail address having positional information of the memory cell, in a test mode;

receiving an external address from a semiconductor memory device, and counting and generating an internal address;

comparing the internal address with the fail address and generating a repair signal; and

replacing the memory cell in which a failure occurred with a redundant cell in response to the repair signal.

13. The repair method of claim 12 , wherein the fail address is replaced with the redundant cell when the integrated circuit exits from the test mode.

14. The repair method of claim 12 , wherein the extracting of the fail address comprises:

outputting a test address which is sequentially counted and generated by a memory controller and input data which is to be written into the memory cell; and

storing the test address corresponding to the memory cell as the fail address in a fail address storage unit, when the input data is not identical to output data read from the memory cell.

15. The integrated circuit of claim 14 , wherein the fail address storage unit comprises a nonvolatile element.

16. The integrated circuit of claim 12 , wherein the repair signal is enabled when the fail address is identical to the internal address.