Signal delay circuit

1. A signal delay circuit comprising:

a voltage detection unit configured to generate a detection signal in response to a result of comparing an external voltage level with a reference voltage, wherein the detection signal is determined by a variation of the external voltage level; and

a signal delay unit configured to control a delay amount of an input signal in response to the detection signal and to include a first delay selector configured to be enabled to select a delay amount having a first delay time in response to the level of the detection signal and a second delay selector configured to be enabled to select a delay amount having a second delay time in response to the level of the detection signal,

wherein the first delay time is set to be larger than the second delay time,

wherein when the detection signal is at a low level, the first delay selector is enabled, and when the detection signal is at a high level, the second delay selector is enabled,

wherein the voltage detection unit generates a high-level detection signal when the external voltage level is lower than the reference voltage.

2. The signal delay circuit according to claim 1 , wherein the first delay selector comprises a first NAND gate configured to receive an inverted detection signal and the input signal.

3. The signal delay circuit according to claim 1 , wherein the second delay selector comprises a second NAND gate configured to receive the detection signal and the input signal.

4. The signal delay circuit according to claim 1 , wherein the signal delay unit comprises:

a first NAND gate configured to receive an inverted detection signal and the input signal;

a first buffer configured to delay an output of the first NAND gate;

a second NAND gate configured to receive the detection signal and the input signal;

a third NAND gate configured to receive an output of the second NAND gate and an output of the first buffer; and

a second buffer configured to delay an output of the third NAND gate and output the delayed signal as an output signal.

5. The signal delay circuit according to claim 4 , wherein the voltage detection unit generates a high-level detection signal when the external voltage level is lower than the reference voltage.

6. A signal delay circuit comprising:

a voltage detection unit configured to detect an external voltage level as a plurality of voltage levels, based on a reference voltage, and generate a multi-bit detection signal;

a decoder configured to decode values of the multi-bit detection signal into a selection signal; and

a signal delay unit configured to control a delay amount of an input signal in response to the selection signal.

7. The signal delay circuit according to claim 6 , wherein the voltage detection unit comprises:

a reference voltage divider configured to divide the reference voltage level into first and second reference voltages; and

a comparator configured to compare the external voltage level with the first and second divided reference voltages and generate a 2-bit detection signal, and

the first divided reference voltage has a higher level than the second divided reference voltage.

8. The signal delay circuit according to claim 7 , wherein, when the external voltage level is lower than the first divided reference voltage, the comparator outputs an upper-bit detection signal having a value of 1 and when the external voltage level is lower than the second divided reference voltage, the comparator outputs a lower-bit detection signal having a value of 1.

9. The signal delay circuit according to claim 6 , wherein the selection signal comprises first to third selection signals,

the decoder selects and outputs the first selection signal when the multi-bit detection signal in which the external voltage level is detected as a first level or more is inputted, selects and outputs the third selection signal when the multi-bit detection signal in which the external voltage level is detected as a second level or less is inputted, and selects and outputs the second selection signal when the multi-bit detection signal in which the external voltage level corresponds to the other voltage levels is inputted, and

the first level is higher than the second level.

10. The signal delay circuit according to claim 9 , wherein the signal delay unit comprises:

a first NAND gate configured to receive the first selection signal and the input signal;

a second NAND gate configured to receive the second selection signal and the input signal;

a third NAND gate configured to receive the third selection signal and the input signal;

a first buffer configured to delay an output of the first NAND gate;

a fourth NAND gate configured to receive an output of the second NAND gate and an output of the first buffer;

a second buffer configured to delay an output of the fourth NAND gate;

a fifth NAND gate configured to receive an output of the third NAND gate and an output of the second buffer; and

a third buffer configured to delay an output of the fifth NAND gate and output the delayed signal as an output signal.

11. The signal delay circuit according to claim 9 , wherein the selection signal comprises first to third selection signals, and

the decoder selects and outputs the first selection signal when the multi-bit detection signal is [00], selects and outputs the second selection signal when the multi-bit detection signal is [10], and selects and outputs the third selection signal when the multi-bit detection signal is [11].

12. The signal delay circuit according to claim 11 , wherein the signal delay unit comprises:

a first delay selector configured to be enabled to select a delay amount having a first delay time in response to the first selection signal;

a second delay selector configured to be enabled to select a delay amount having a second delay time in response to the second selection signal; and

a third delay selector configured to be enabled to select a delay amount having a third delay time in response to the third selection signal, and

the first delay time is set to be larger than the second delay time, and the second delay time is set to be larger than the third delay time.

13. The signal delay circuit according to claim 12 , wherein the first delay selector comprises a first NAND gate configured to receive the first selection signal and the input signal.

14. The signal delay circuit according to claim 12 , wherein the second delay selector comprises a second NAND gate configured to receive the second selection signal and the input signal.

15. The signal delay circuit according to claim 12 , wherein the third delay selector comprises a third NAND gate configured to receive the third selection signal and the input signal.