Semiconductor wafer plating bus
View Patent ↗A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.
1. A semiconductor wafer, comprising:
a die adjacent to a saw street;
an edge seal along a perimeter of the die, wherein the edge seal includes a first conductive layer formed in a last interconnect layer of the die;
a bond pad formed as part of one of a group consisting of the last interconnect layer and a metal deposition layer above the last interconnect layer;
a plating bus within the saw street;
a trace connected to the bond pad and to the plating bus by a manner comprising one of a group consisting of (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer and (2) through the edge seal and insulated from the edge seal.
2. The semiconductor wafer of claim 1 , wherein the bond pad further comprises a plated layer over the metal deposition layer of the bond pad.
3. The semiconductor wafer of claim 2 , wherein the plated layer comprises nickel.
4. The semiconductor wafer of claim 2 , wherein the trace is connected to the bond pad and to the plating bus by the manner comprising over the edge seal, insulated from the edge seal, and formed as part of the metal deposition layer.
5. The semiconductor wafer of claim 4 , wherein the last interconnect layer comprises copper.
6. The semiconductor wafer of claim 5 , wherein the bond pad is part of both the last interconnect layer and the metal deposition layer and comprises a first portion of the last metal interconnect layer.
7. The semiconductor wafer of claim 6 , wherein the bond pad has a portion of the last metal interconnect layer and a portion of the metal deposition layer in which the portion of the last metal interconnect layer extends laterally beyond the portion of the metal deposition layer.
8. The semiconductor wafer of claim 7 , wherein the trace is coupled to the portion of the last metal interconnect layer.
9. The semiconductor wafer of claim 2 , wherein the trace is connected to the bond pad and to the plating bus by the manner comprising through the edge seal and insulated from the edge seal.
10. The semiconductor wafer of claim 9 , wherein the edge seal comprises a portion from each of a plurality of metal interconnect layers including the last interconnect layer.
11. The semiconductor wafer of claim 10 , wherein the trace comprises a portion of an additional metal interconnect layer, wherein the portion of the additional metal interconnect layer extends laterally past the edge seal on a first side toward the die and extends laterally past the edge seal on a second side toward the plating bus.
12. The semiconductor wafer of claim 11 , wherein the trace further comprises a first via connected to a first portion of the last interconnect layer and a second via connected to a second portion of the last interconnect layer, wherein the first portion of the last interconnect layer is connected to the bond pad and the second portion of the last interconnect layer is connected to the plating bus.