Granted Patent B2

US 8,658,497 · App. 13/343,331 · Granted Feb 25, 2014

Abstract

Claims (43)

1. A method of forming an NVM cell and a logic transistor using a semiconductor substrate, comprising:

in a non-volatile memory (NVM) region, forming over the semiconductor substrate a first high-k gate dielectric, a metal select gate, and a first dielectric layer, wherein the metal select gate is on the first high-k dielectric, a top surface of the first dielectric layer is substantially aligned with a top surface of the metal select gate, and the first dielectric layer has a first opening in which the metal select gate is present in the first opening;

in a logic region, forming over the semiconductor substrate a second high-k gate dielectric, a metal logic gate, a source and a drain in the semiconductor substrate, and a second dielectric layer, wherein the metal logic gate is on the second high-k dielectric, a top surface of the second dielectric layer is substantially aligned with a top surface of the metal logic gate, and the second dielectric layer has a second opening in which the metal logic gate is present in the second opening;

forming a hard mask over the NVM region and the logic region;

removing the first dielectric layer in the NVM region while leaving the second dielectric layer in the logic region, wherein the forming the hard mask is performed prior to the removing the first dielectric layer;

forming a charge storage layer comprising metal nanocrystals over the NVM region including over the metal select gate;

forming a metal layer over the charge storage layer;

patterning the metal layer to form a metal control gate; and

etching the charge storage layer to leave a remaining portion of the storage layer aligned to the metal control gate.

2. The method of claim 1 , wherein:

the forming the charge storage layer is further characterized by forming the charge storage layer over the second dielectric layer and the metal logic gate; and

the etching the storage layer is further characterized by removing the charge storage layer over the second dielectric and the metal logic gate.

3. The method of claim 2 , wherein:

the step of forming the metal layer is further characterized by forming the metal layer over the logic region; and

the step of patterning the metal layer is further characterized by removing the metal layer over the logic region.

4. The method of claim 3 , wherein the forming the first dielectric layer and forming the second dielectric layer are further characterized as forming the first dielectric and the second dielectric layers simultaneously of a same material.

5. The method of claim 1 , further comprising forming a first silicide region on the source and a second silicide region on the drain of the logic transistor prior to the forming of the second dielectric layer.

6. The method of claim 5 , further comprising:

forming a sidewall spacer around the metal logic gate prior to the forming the second dielectric layer.

7. The method of claim 6 , further comprising:

forming a liner around the metal logic gate prior to the forming the sidewall spacer.

8. The method of claim 1 , further comprising removing the hard mask from over the NVM region while leaving the hard mask over the logic region prior to removing the first dielectric layer.

9. The method of claim 1 , wherein the forming the metal select gate and the forming the logic gate comprise a replacement gate process.

10. The method of claim 1 , wherein:

the forming the logic gate comprises forming a stack comprising a work-function-setting metal on the first high-k gate dielectric and a top metal over the work-function-setting metal.

11. The method of claim 1 , wherein:

the forming the metal logic gate comprises forming a stack having a first composition and the forming the metal select gate comprises forming a stack having a second composition wherein the first composition is different from the second composition.

12. The method of claim 1 , wherein the forming the charge storage layer comprises:

forming a base dielectric layer;

forming the metal nanocrystals on the base layer; and

forming a fill dielectric layer around and over the metal nanocrystals.

13. A method, comprising:

forming a logic transistor having a metal logic gate, a high-k gate dielectric, a sidewall spacer around the metal logic gate, and silicided source/drains in a logic region of a semiconductor substrate and a metal select gate of a non-volatile memory (NVM) cell on a high-k dielectric and in an NVM portion of the semiconductor substrate using a dielectric that is left around the metal logic gate and the metal select gate, wherein a top surface of the dielectric is substantially aligned to a top surface of the metal select gate and a top surface of the metal logic gate;

forming a hard mask over the NVM region and the logic region;

removing the dielectric from around the metal select gate, wherein the forming the hard mask is performed prior to the removing the dielectric;

forming a charge storage layer comprising metal nanocrystals over the logic region and the NVM region;

forming a metal layer over the logic region and the NVM region;

patterning the metal layer over the NVM region to form a metal control gate over a portion of the metal select gate and a portion of the substrate and removing the metal layer from the logic region;

etching the charge storage layer to leave the charge storage layer under and aligned with the metal control gate and to remove the charge storage layer over the logic region; and

forming source/drain regions in the substrate in the NVM region adjacent to the metal control gate and to the metal select gate.

14. The method of claim 13 further comprising:

siliciding the source/drain regions in the substrate in the NVM region; and

removing the hard mask after the siliciding the source/drain regions in the substrate in the NVM region.

Assignments (21)