Device and methods for forming partially self-aligned trenches

1. A method of making a semiconductor device, the method comprising:

forming a gate structure over a semiconductor substrate;

forming a sidewall spacer adjoining a sidewall of the gate structure;

forming an etch stop layer over the sidewall spacer;

forming a first interlayer dielectric (ILD) layer over the etch stop layer;

planarizing the first ILD layer;

forming an etch buffer layer over the planarized first ILD layer;

forming a second ILD layer over the etch buffer layer;

forming trenches in the second ILD layer and the etch buffer layer;

filling the trenches with a conductive material; and

planarizing the conductive material.

2. The method of claim 1 , wherein the etch buffer layer comprises silicon nitride, the ILD layer comprises silicon oxide, or both.

3. The method of claim 1 , further comprising replacing the gate structure with a metal gate after planarizing the first ILD layer.

4. The method of claim 1 , wherein the etch buffer layer has an etch rate that is lower than the first ILD layer.

5. The method of claim 1 , further comprising etching-back the first ILD layer to reduce thickness of the first ILD layer before forming the etch buffer layer.

6. The method of claim 1 , wherein the etch buffer layer comprises an edge disposed on an upper portion of the etch stop layer, and wherein a width between adjacent edges is narrower than a width between adjacent sidewall spacers.

7. The method of claim 6 , wherein the trenches are partially self-aligned along the adjacent edges.

8. The method of claim 6 , wherein the etch buffer layer slows down lateral etching during formation of the trench.

9. The method of claim 6 , wherein the etch buffer layer is formed by plasma-enhanced chemical vapor deposition, physical vapor deposition, chemical vapor deposition, or a combination thereof.

10. A method of making a semiconductor device, the method comprising:

forming a gate structure over a semiconductor substrate;

forming a sidewall spacer adjoining a sidewall of the gate structure;

forming an etch stop layer over the sidewall spacer;

forming a first silicon oxide layer over the etch stop layer;

planarizing the first silicon oxide layer;

forming a silicon nitride layer over the planarized first silicon oxide layer by plasma-enhanced chemical vapor deposition, physical vapor deposition, chemical vapor deposition, or a combination thereof;

forming a second silicon oxide layer over the silicon nitride layer;

forming trenches in the second silicon oxide layer and silicon nitride layer;

filling the trenches with a conductive material; and

planarizing the conductive material.

11. The method of claim 10 , further comprising etching-back the first silicon oxide layer to reduce thickness of the first silicon oxide layer before forming the silicon nitride layer.

12. The method of claim 10 , wherein adjacent edges of the silicon nitride layer define the critical dimension (CD) of the trenches, and the trenches have a smaller CD than the CD between the bases of adjacent gate structures.

13. The method of claim 10 , wherein an upper portion of the trenches is adjacent to the silicon nitride layer and a bottom portion of the trenches is adjacent the first silicon oxide layer.

14. A method of making a semiconductor device, comprising:

providing a semiconductor substrate;

forming a plurality of gate structures over the semiconductor substrate;

forming a plurality of sidewall spacers over the gate structures;

disposing an etch stop layer over the sidewall spacers;

disposing an interlayer dielectric (ILD) layer on a bottom portion of the etch stop layer;

disposing an etch buffer layer on an upper portion of the etch stop layer; and

forming a plurality of metal plugs between the gate structures, wherein an upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.

15. The method of claim 14 , wherein the etch stop layer, the etch buffer layer, or both comprise silicon nitride.

16. The method of claim 14 , wherein the etch buffer layer has an etch rate that is lower than the ILD layer.

17. The method of claim 14 , wherein the metal plugs comprise tungsten.

18. The method of claim 14 , wherein adjacent edges of the etch buffer layer define a critical dimension (CD) of the metal plugs.

19. The method of claim 18 , wherein the metal plugs are partially self-aligned along the adjacent edges.

20. The method of claim 18 , wherein a width between the adjacent edges is narrower than a width between bases of adjacent gate structures.