Strain engineering in three-dimensional transistors based on strained isolation material
In a three-dimensional transistor configuration, a strain-inducing isolation material is provided, at least in the drain and source areas, thereby inducing a strain, in particular at and in the vicinity of the PN junctions of the three-dimensional transistor. In this case, superior transistor performance may be achieved, while in some illustrative embodiments even the same type of internally stressed isolation material may result in superior transistor performance of P-channel transistors and N-channel transistors.
1. A method of forming a transistor device, comprising:
forming at least one semiconductor fin in a drain area and a source area of a semiconductor region of a transistor, said drain area and said source area being laterally separated by a channel area, said at least one semiconductor fin being elongated along a length direction and having sidewalls and a top surface;
forming a strain-inducing isolation material laterally adjacent to at least a portion of sidewalls of said at least one semiconductor fin, said isolation material inducing a strain in said at least one semiconductor fin in said drain and source areas perpendicular to said length direction;
forming a masking layer above said strain-inducing isolation material and said at least one fin, said masking layer having a gate-shaped opening corresponding to a lateral size of a gate electrode for said device, said gate-shaped opening being positioned above said channel area of said device;
performing an etching process through said gate-shaped opening to remove at least a portion of said strain-inducing isolation material positioned below said gate-shaped opening in said masking layer and thereby expose at least a portion of said sidewalls of said at least one fin; and
with said masking layer in position, performing at least one process operation through said gate-shaped opening to form at least a gate insulation layer and a gate electrode around said at least one fin.
2. The method of claim 1 , wherein forming said at least one semiconductor fin comprises forming said at least one semiconductor fin so as to extend through said channel area.
3. The method of claim 1 , wherein performing said etching process through said gate-shaped opening to remove at least a portion of said strain-inducing isolation material positioned below said gate-shaped opening comprises performing said etching process through said gate-shaped opening to remove substantially all of said strain-inducing isolation material positioned below said gate-shaped opening so as to thereby expose a surface of said semiconductor region.
4. The method of claim 1 , wherein performing said etching process through said gate-shaped opening to remove at least a portion of said strain-inducing isolation material positioned below said gate-shaped opening comprises performing said etching process through said gate-shaped opening to remove less that an entirety of said strain-inducing isolation material positioned below said gate-shaped opening so as to thereby define a recessed surface of said strain-inducing isolation material positioned below said gate-shaped opening.
5. A method of forming a transistor device, comprising:
forming at least one semiconductor fin in a drain area and a source area of a semiconductor region of a transistor, said drain area and said source area being laterally separated by a channel area, said at least one semiconductor fin being elongated along a length direction and having sidewalls and a top surface;
forming a strain-inducing isolation material that is positioned within said channel area and laterally adjacent to at least a portion of sidewalls of said at least one semiconductor fin, said isolation material inducing a strain in said at least one semiconductor fin in said drain and source areas perpendicular to said length direction;
forming a sacrificial gate structure above said strain-inducing isolation material and said at least one fin, said sacrificial gate structure being positioned above said channel region of said device;
forming a sidewall spacer adjacent said sacrificial gate structure;
forming a layer of insulating material adjacent said sidewall spacer;
removing said sacrificial gate structure to thereby define a gate opening defined by said spacers that exposes an upper surface of said strain-inducing isolation material;
performing an etching process through said gate opening to remove at least a portion of said strain-inducing isolation material positioned below said gate opening and thereby expose at least a portion of said sidewalls of said at least one fin; and
forming final gate structure within said gate opening and around said at least one fin, said final gate structure comprising at least a gate insulation layer and a gate electrode.
6. The method of claim 5 , wherein forming said at least one semiconductor fin comprises forming said at least one semiconductor fin so as to extend through said channel area.
7. The method of claim 5 , wherein performing said etching process through said gate opening to remove at least a portion of said strain-inducing isolation material positioned below said gate opening comprises performing said etching process through said gate opening to remove substantially all of said strain-inducing isolation material positioned below said gate opening so as to thereby expose a surface of said semiconductor region.
8. The method of claim 5 , wherein performing said etching process through said gate opening to remove at least a portion of said strain-inducing isolation material positioned below said gate opening comprises performing said etching process through said gate opening to remove less that an entirety of said strain-inducing isolation material positioned below said gate opening so as to thereby define a recessed surface of said strain-inducing isolation material positioned below said gate opening.