Anti-fuse control circuit

1. An anti-fuse control circuit, comprising:

a first power supply voltage application unit configured to selectively apply first power supply voltage to an output node in response to a power up signal;

a second power supply voltage application unit configured to selectively apply second power supply voltage to the output node in response to a program signal; and

a control unit configured to receive the power up signal and the program signal and control a connection between the output node and an anti-fuse in response to the power up signal and the program signal.

2. The anti-fuse control circuit of claim 1 , further comprising a latch unit configured to latch and output an output signal of the output node.

3. The anti-fuse control circuit of claim 1 , wherein the control unit applies the second power supply voltage to the anti-fuse when the program signal is activated.

4. The anti-fuse control circuit of claim 1 , wherein the control unit selectively applies the first power supply voltage to the anti-fuse in response to the power up signal when the program signal is inactivated.

5. The anti-fuse control circuit of claim 4 , wherein the control unit blocks the first power voltage from being applied to the anti-fuse when the power up signal is activated.

6. The anti-fuse control circuit of claim 4 , wherein the control unit applies the first power supply voltage to the anti-fuse for a predetermined length of time from the inactivated timing when the power up signal is inactivated.

7. The anti-fuse control circuit of claim 1 , wherein the control unit includes:

a fuse sense enable signal generator that generates a fuse sense enable signal controlling a connection between the output node and the anti-fuse in response to the power up signal and the program signal; and

a switch unit that selectively connects the output node with the anti-fuse in response to the fuse sense enable signal.

8. The anti-fuse control circuit of claim 7 , wherein the fuse sense enable signal generator includes:

an inverter that inverts and outputs the power up signal;

a first delay device that delays and outputs the output signal of the inverter by a predetermined length of time;

a NOR gate that logically operates the power up signal and an output signal of the first delay device;

a second delay device that delays and outputs the output of the NOR gate by predetermined length of time;

a latch that latches the output signal of the NOR gate and the output signal of the second delay device; and

a NAND gate that logically operates the output signal of the latch and the program signal to generate the fuse sense enable signal.

9. The anti-fuse control circuit of claim 7 , wherein the switch unit includes:

an inverter that inverts and outputs the fuse sense enable signal;

a PMOS transistor that is connected between the output node and the anti-fuse to receive the output signal of the inverter; and

an NMOS transistor that is connected between the output node and the antifuse to receive the fuse sense enable signal.

10. The anti-fuse control circuit of claim 1 , wherein the first power supply voltage application unit includes:

an inverter that inverts and outputs the power up signal; and

a first PMOS transistor that receives the output signal of the inverter through a gate thereof and selectively applies the first power supply voltage to the output node.

11. The anti-fuse control circuit of claim 1 , wherein the second power supply voltage application unit includes a first PMOS transistor that receives the program signal through a gate thereof and selectively applies the second power supply voltage to the output node.