Method and apparatus for performing model-based OPC for pattern decomposed features
A method for decomposing a target circuit pattern containing features to be imaged into multiple patterns. The process includes the steps of separating the features to be printed into a first pattern and a second pattern; performing a first optical proximity correction process on the first pattern and the second pattern; determining an imaging performance of the first pattern and the second pattern; determining a first error between the first pattern and the imaging performance of the first pattern, and a second error between the second pattern and the imaging performance of said second pattern; utilizing the first error to adjust the first pattern to generate a modified first pattern; utilizing the second error to adjust the second pattern to generate a modified second pattern; and applying a second optical proximity correction process to the modified first pattern and the modified second pattern.
1. A method of correcting a design layout to be imaged using a multiple-exposure optical lithography process, the method comprising:
(a) separating a feature of the design layout into a first pattern and a second pattern, the first pattern to be imaged by a first exposure, and the second pattern to be imaged by a second exposure;
(b) performing a first correction process on the first pattern, and a second correction process on the second pattern to extract overlap area between the first pattern and the second pattern;
(c) adding the extracted overlap area to each of the first pattern and the second pattern; and
(d) performing a third correction process on the first pattern including the extracted overlap area, and a fourth correction process on the second pattern including the extracted overlap area.
2. The method of claim 1 , wherein the method further comprises:
(e) combining the corrected first pattern and the corrected second pattern to create a corrected version of the original feature of the design layout; and
(f) verifying that the corrected version of the original feature improves overall imaging performance of the multiple-exposure optical lithography process.
3. The method of claim 2 , wherein steps (b) to (f) are repeated until the overall imaging performance of the multiple-exposure optical lithography process meets a desired quality.
4. The method of claim 2 , wherein the method further comprises, after the verification step:
(g) generating a first mask corresponding to the corrected first pattern, and a second mask corresponding to the corrected second pattern.
5. The method of claim 1 , wherein one or more of the first correction process, the second correction process, the third correction process, and the fourth correction process are done using reference parameters for optical proximity correction (OPC).
6. The method of claim 1 , wherein one or both of the first correction process and the second correction process are done using reference parameters for optical proximity correction (OPC), and, one or both of the third correction process and the fourth correction process are done using parameters dynamically adjusted with respect to the reference parameters for optical proximity correction (OPC).
7. The method of claim 1 , wherein in step (a), the feature is separated based on line width or based on spacing between two lines in the feature.
8. The method of claim 1 , wherein the overlap area is extracted in step (b) based on one or more of: Boolean operation and geometry of the feature.
9. The method of claim 1 , wherein the third correction process and the fourth correction process are performed based on imaging errors estimated from the first correction process and the second correction process, respectively.
10. The method of claim 9 , wherein the estimated imaging errors are converted into polygons that are added to the first pattern and the second pattern.
11. The method of claim 1 , wherein prior to step (a), areas with relatively dense features are identified in the design layout.
12. The method of claim 1 , wherein the design layout comprises a layout of an entire chip or a portion thereof.
13. The method of claim 1 , wherein the steps are performed in a model-based simulation process.
14. A non-transitory computer-readable storage media storing a computer program having computer-executable instructions for causing a computer to use a model-based simulation process to correct a design layout to be imaged by multiple-exposure optical lithography process, the instructions causing the computer to perform the method of claim 1 .
15. The computer program product of claim 14 , wherein the instructions further causes the computer to perform the following steps:
combining the corrected first pattern and the corrected second pattern to create a corrected version of the original feature of the design layout; and
verifying that the corrected version of the original feature improves overall imaging performance of the multiple-exposure optical lithography process.
16. A computer-implemented system using a model-based simulation process to correct a design layout to be imaged using a multiple-exposure optical lithography process, the system comprising a computer processor performing the following steps:
(a) separating a feature of the design layout into a first pattern and a second pattern, the first pattern to be imaged by a first exposure, and the second pattern to be imaged by a second exposure;
(b) performing a first correction process on the first pattern, and a second correction process on the second pattern to extract overlap area between the first pattern and the second pattern;
(c) adding the extracted overlap area to each of the first pattern and the second pattern; and
(d) performing a third correction process on the first pattern including the extracted overlap area, and a fourth correction process on the second pattern including the extracted overlap area.
17. The system of claim 16 , wherein the computer processor further performs:
(e) combining the corrected first pattern and the corrected second pattern to create a corrected version of the original feature of the design layout; and
(f) verifying that the corrected version of the original feature improves overall imaging performance of the multiple-exposure optical lithography process.
18. The system of claim 16 , wherein one or more of the first correction process, the second correction process, the third correction process, and the fourth correction process are done using reference parameters for optical proximity correction (OPC).
19. The system of claim 16 , wherein one or both of the first correction process and the second correction process are done using reference parameters for optical proximity correction (OPC), and, one or both of the third correction process and the fourth correction process are done using parameters dynamically adjusted with respect to the reference parameters for optical proximity correction (OPC).
20. The system of claim 16 , wherein the overlap area is extracted in step (b) based on one or more of: Boolean operation and geometry of the feature.
21. The system of claim 16 , wherein the third correction process and the fourth correction process are performed based on imaging errors estimated from the first correction process and the second correction process, respectively.
22. The system of claim 21 , wherein the estimated imaging errors are converted into polygons that are added to the first pattern and the second pattern.