IP Library Granted Patent US 8,912,667
Granted Patent B2
US 8,912,667 · App. 13/362,636 · Granted Dec 16, 2014

Packaged integrated circuit using wire bonds

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Quick Facts
Patent No.
US 8,912,667
App. No.
13/362,636
Granted
Dec 16, 2014
Kind
B2
Abstract

A semiconductor device includes an integrated circuit die on a substrate. A first subset of wire bonds is between the substrate and the die. A second subset of wire bonds is between the substrate and the die. A dielectric material coats the first subset of the wire bonds along a majority of length of the first subset of the wire bonds. A medium is in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

Claims (53)

1. A semiconductor device comprising:

a substrate;

an integrated circuit die on the substrate;

a first subset of wire bonds between the substrate and the integrated circuit die;

a second subset of wire bonds between the substrate and the integrated circuit die;

a dielectric material coating the first subset of the wire bonds along a majority of length of the first subset of the wire bonds, wherein the dielectric material includes a poregen material; and

a medium in contact with the second subset of the wire bonds along a majority of length of the second subset of the wire bonds.

2. The semiconductor device of claim 1 , wherein:

the medium comprises one of a group consisting of a vacuum, air, and an encapsulating material.

3. The semiconductor device of claim 1 , wherein:

the first subset of the wire bonds includes one of a group consisting of one signal wire bond and one ground wire bond, a power wire bond and a ground wire bond, two signal wire bonds and one ground wire bond, and two signal wire bonds and two ground wire bonds.

4. The semiconductor device of claim 1 , wherein:

the dielectric material is one of a group consisting of a low-K dielectric material, a high-K dielectric material, and a combination of the low-K and high-K dielectric materials.

5. The semiconductor device of claim 1 , wherein:

capacitance of a combination of the first dielectric material and the first subset of the plurality of wire bonds is different from capacitance of the first subset of the plurality of wire bonds.

6. The semiconductor device of claim 1 , wherein:

the dielectric material electrically decouples the first subset of wire bonds from the second subset of wire bonds.

7. The semiconductor device of claim 1 having a further characterization comprising:

one of a group consisting of a first one of the wire bonds is positioned over a second one of the wire bonds, and a first one of the wire bonds is positioned adjacent a second one of the wire bonds.

8. The semiconductor device of claim 1 , wherein:

the medium comprises a second dielectric material, wherein the dielectric material and the second dielectric material are electrically decoupled from one another.

9. A semiconductor device comprising:

a first surface;

a second surface;

a plurality of wire bonds between the first surface and the second surface; and

a dielectric material coating a first subset of the wire bonds, wherein properties of the dielectric material are different from a medium in contact with a second subset of the wire bonds so that the first subset of the wire bonds is electrically decoupled from a second subset of the plurality of wire bonds, wherein the dielectric material coats the first subset of the wire bonds for a majority of a length of the first subset of wire bonds, and wherein the dielectric material includes a poregen material.

10. The semiconductor device of claim 9 , having a further characterization comprising:

one of a group consisting of (1) the first surface is a first integrated circuit die and the second surface is a second integrated circuit die and (2) the first surface is an integrated circuit and the second surface is a substrate.

11. The semiconductor device of claim 9 , wherein:

the medium comprises one of a group consisting of the dielectric material, a second dielectric material, a vacuum, air, and an encapsulating material.

12. The semiconductor device of claim 9 , wherein:

the first subset of the wire bonds includes one of a group consisting of:

one signal wire bond and one ground wire bond,

two signal wire bonds and two ground wire bonds,

a power wire bond and a ground wire bond, and

two signal wire bonds and one ground wire bond.

13. The semiconductor device of claim 9 , wherein:

the dielectric material comprises one of a group consisting of a low-K dielectric material, a high-K dielectric material, and a combination of the low-K and high-K dielectric materials.

14. The semiconductor device of claim 9 , wherein:

the dielectric material changes capacitance of the first subset of the wire bonds.

15. The semiconductor device of claim 9 further characterized by one of a group consisting of:

a first one of the wire bonds is positioned over a second one of the wire bonds, and

the first one of the wire bonds is positioned laterally adjacent the second one of the wire bonds.

16. A method for fabricating a semiconductor device, the semiconductor device includes a plurality of wire bonds between a first set of contact pads and a second set of contact pads, the method comprising:

dispensing a first dielectric coating on a first subset of the plurality of wire bonds, wherein the coating covers a majority of length of the first subset of the plurality of wire bonds and capacitance of a combination of the first dielectric coating and the first subset of the plurality of wire bonds is different from capacitance of the first subset of the plurality of wire bonds, and wherein the dielectric material includes a poregen material.

17. The method of claim 16 wherein:

the first subset of the plurality of wire bonds includes one of a group consisting of:

one signal wire bond and one ground wire bond,

two signal wire bonds and two ground wire bonds,

a power wire bond and a ground wire bond, and

two signal wire bonds and one ground wire bond.

18. The method of claim 16 further comprising:

dispensing a second dielectric coating on a second subset of the plurality of wire bonds, wherein the second dielectric coating covers more than a majority of length of the second subset of the plurality of wire bonds and capacitance of a combination of the second dielectric coating and the second subset of the plurality of wire bonds is different from capacitance of the second subset of the plurality of wire bonds.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0455 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0521 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0476 →
CORRECTIVE ASSIGNMENT TO CORRECT TO ADD INVENTOR CHU-CHUNG LEE PREVIOUSLY RECORDED AT REEL: 027628 FRAME: 0077. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Nov 14, 2014
From: WENZEL, ROBERT J.; HESS, KEVIN J.; LEE, CHU-CHUNG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034238/0821 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030256/0582 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 030256/0670 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030256/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2012
From: WENZEL, ROBERT J.; HESS, KEVIN J.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 027628/0077 →