Semiconductor device having different non-volatile memories having nanocrystals of differing densities and method therefor
View Patent ↗A method for forming a semiconductor device includes forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and, after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
1. A method for forming a semiconductor device, comprising:
forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region and has a first density; and
after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region, wherein the first plurality of nanocrystals together with the second plurality of nanocrystals in the second region result in a second density, wherein the second density is greater than the first density.
2. The method of claim 1 , further comprising:
forming a first memory transistor in the first region, wherein the first memory transistor comprises a first charge storage layer, wherein the first charge storage layer includes a first portion of the first plurality of nanocrystals; and
forming a second memory transistor in the second region, wherein the second memory transistor comprises a second charge storage layer, wherein the second charge storage layer includes a second portion of the first plurality of nanocrystals and a portion of the second plurality of nanocrystals, wherein a nanocrystal density of the second charge storage layer is greater than a nanocrystal density of the first charge storage layer.
3. The method of claim 2 , wherein the nanocrystal density of the first charge storage layer corresponds a maximum nanocrystal density of memory transistors within the first region and the nanocrystal density of the second charge storage layer corresponds to a minimum nanocrystal density of memory transistors within the second region.
4. The method of claim 1 , wherein the step of forming the second plurality of nanocrystals comprises:
forming an insulating layer over the substrate in the first region and the second region;
implanting a material into the insulating layer, wherein the implanting is performed in the second region and not the first region; and
annealing the material to form the second plurality of nanocrystals in the insulating layer.
5. The method of claim 4 , wherein the step of forming the insulating layer is performed such that the insulating layer is formed over the first plurality of nanocrystals.
6. The method of claim 4 , wherein forming the first plurality of nanocrystals comprises forming the first plurality of nanocrystals on the insulating layer prior to the step of implanting the material.
7. The method of claim 1 , wherein an average diameter of the first plurality of nanocrystals is greater than an average diameter of the second plurality of nanocrystals.
8. The method of claim 1 , wherein prior to the step of forming the second plurality of nanocrystals, the method further comprises:
removing a portion of the first plurality of nanocrystals from a third region of the substrate, wherein the step of forming the second plurality of nanocrystals is performed such that the second plurality of nanocrystals is not formed in the third region; and
forming a logic transistor in the third region.
9. The method of claim 1 , further comprising:
after the step of forming the second plurality of nanocrystals, removing a portion of each of the first plurality of nanocrystals and second plurality of nanocrystals from a third region of the substrate; and
forming a logic transistor in the third region.
10. A method for forming a semiconductor device, comprising:
forming a first plurality of nanocrystals over a surface of a substrate having a first region and a second region, wherein the first plurality of nanocrystals is formed in the first region and the second region;
after forming the first plurality of nanocrystals, forming a second plurality of nanocrystals over the surface of the substrate in the second region and not the first region;
forming a first memory transistor in the first region, wherein the first memory transistor comprises a first charge storage layer, wherein the first charge storage layer includes a first portion of the first plurality of nanocrystals and has a first nanocrystal density; and
forming a second memory transistor in the second region, wherein the second memory transistor comprises a second charge storage layer, wherein the second charge storage layer includes a second portion of the first plurality of nanocrystals and a portion of the second plurality of nanocrystals, wherein the second charge storage layer has a second nanocrystal density that is greater than the first nanocrystal density.
11. The method of claim 10 , wherein the step of forming the second plurality of nanocrystals comprises:
forming an insulating layer over the substrate in the first region and the second region;
implanting a material into the insulating layer, wherein the implanting is performed in the second region and not the first region; and
annealing the material to form the second plurality of nanocrystals in the insulating layer.
12. The method of claim 11 , wherein the step of forming the insulating layer is performed such that the insulating layer is formed over the first plurality of nanocrystals.
13. The method of claim 11 , wherein forming the first plurality of nanocrystals comprises forming the first plurality of nanocrystals on the insulating layer prior to the step of implanting the material.
14. The method of claim 10 , wherein prior to the step of forming the second plurality of nanocrystals, the method further comprises:
removing a portion of the first plurality of nanocrystals from a third region of the substrate, wherein the step of forming the second plurality of nanocrystals is performed such that the second plurality of nanocrystals is not formed in the third region; and
forming a logic transistor in the third region.
15. The method of claim 10 , further comprising:
after the step of forming the second plurality of nanocrystals, removing a portion of each of the first plurality of nanocrystals and second plurality of nanocrystals from a third region of the substrate; and
forming a logic transistor in the third region.
16. The method of claim 10 , wherein an average nanocrystal density of all devices in the second region is approximately 20% greater than an average nanocrystal density of all devices in the first region.
17. A semiconductor device, comprising:
a first plurality of memory transistors located in a first continuous region of a semiconductor substrate, wherein the first plurality of memory transistors comprises at least 1000 memory transistors, wherein each memory transistor of the first plurality of memory transistors comprises a charge storage layer having nanocrystals, and wherein the first plurality of memory transistors has a first average density of nanocrystals; and
a second plurality of memory transistors located in a second continuous region of the semiconductor substrate, separate from the first continuous region, wherein the second plurality of memory transistors comprises at least 1000 memory transistors, wherein each memory transistor of the second plurality of memory transistors comprises a charge storage layer having nanocrystals, and wherein the second plurality of memory devices has a second average density of nanocrystals that is at least 20% greater than the first average density.
18. The semiconductor device of claim 17 , wherein any memory transistor of the first plurality of memory transistors has an average nanocrystal density that is less than an average nanocrystal density of each memory transistor of the second plurality of memory transistors.
19. The semiconductor device of claim 17 , wherein within each memory transistor of the second plurality of memory transistors, the charge storage layer comprises:
a dielectric layer over the semiconductor substrate in which a first portion of nanocrystals is located; and
a second portion of nanocrystals located on the dielectric layer.
20. The semiconductor device of claim 17 , further comprising:
a plurality of logic transistors in a third region of the semiconductor substrate, wherein nanocrystals are not present the third region.