IP Library Granted Patent US 8,943,112
Granted Patent B2
US 8,943,112 · App. 13/363,517 · Granted Jan 27, 2015

Sampling/quantization converters

Inventor: Christopher Pagnanelli (Huntington Beach, CA)
Assignee: Syntropy Systems, LLC
H03M3/468H03M3/422H03M3/436
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,943,112
App. No.
13/363,517
Granted
Jan 27, 2015
Kind
B2
Abstract

Provided are, among other things, systems, apparatuses, methods and techniques for converting a continuous-time, continuously variable signal into a sampled and quantized signal. One such apparatus includes an input line for accepting an input signal that is continuous in time and continuously variable, multiple processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. Each of the processing branches includes a continuous-time quantization-noise-shaping circuit, a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, a digital bandpass filter coupled to an output of the sampling/quantization circuit, and a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit. A center frequency of the digital bandpass filter in each the processing branch corresponds to a minimum in a quantization noise transfer function for the continuous-time quantization-noise-shaping circuit in the same processing branch.

Claims (50)

1. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:

an input line for accepting an input signal that is continuous in time and continuously variable;

a plurality of processing branches coupled to the input line, each of said processing branches including: (a) a continuous-time quantization-noise-shaping circuit, (b) a sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, (c) a digital bandpass filter coupled to an output of the sampling/quantization circuit, and (d) a line coupling the output of the sampling/quantization circuit back into the continuous-time quantization-noise-shaping circuit; and

an adder coupled to outputs of the plurality of processing branches,

wherein a frequency band selected by the digital bandpass filter in each said processing branch corresponds to a minimum in a quantization noise transfer function for the continuous-time quantization-noise-shaping circuit in the same processing branch, and

wherein each of said digital bandpass filters includes: (a) a quadrature frequency downconverter that has in-phase and quadrature outputs, (b) a first moving-average filter coupled to the in-phase output of the quadrature frequency downconverter, (c) a second moving-average filter coupled to the quadrature output of the quadrature frequency downconverter, and (d) a quadrature frequency upconverter coupled to outputs of the first and second moving-average filters.

2. An apparatus according to claim 1 , wherein at least one of the moving-average filters is implemented as a recursive structure.

3. An apparatus according to claim 2 , wherein said at least one moving-average filter recursive structure incorporates a differentiator transfer function with a difference delay greater than one sample period.

4. An apparatus according to claim 1 , wherein at least one of the moving-average filters is comprised of at least three cascaded moving-average components.

5. An apparatus according to claim 4 , wherein a number of samples averaged by each of the cascaded moving-average components is independently programmable to vary a bandwidth of the corresponding digital bandpass filter.

6. An apparatus according to claim 1 , wherein at least one of the digital bandpass filters is implemented as a polyphase decomposition structure.

7. An apparatus according to claim 6 , wherein a polyphase decomposition factor, m, of the polyphase decomposition structure is a submultiple of the total number of processing branches, M.

8. An apparatus according to claim 1 , wherein the moving-average filter is comprised of a number of cascaded moving-average filter stages, wherein each of the stages averages the same number of samples, and wherein the number of stages is greater than one and other than one plus an effective noise-shaping order of the continuous-time quantization-noise-shaping circuit response.

9. An apparatus according to claim 8 , wherein the moving-average filter is comprised of cascaded moving-average filter stages that collectively provide spectral minima at frequencies other than multiples of a conversion rate of said apparatus.

10. An apparatus according to claim 8 , wherein the number of moving-average stages is zero, two, three, or four plus an effective noise-shaping order of a response of the continuous-time quantization-noise-shaping circuit.

11. An apparatus according to claim 1 , wherein the moving-average filter is comprised of cascaded moving-average filter stages, and wherein at least one of the stages averages a number of samples that is different by more than one from a number of samples averaged by at least one of the other stages.

12. An apparatus according to claim 11 , wherein the number of samples averaged by one of the stages is different from at least one of the other stages by more than ¼·M·N and less than 2·M·N, where N is an excess-rate oversampling ratio of said apparatus and M is the number of processing branches.

13. An apparatus according to claim 1 , wherein the moving-average filter is comprised of cascaded moving-average filter stages having an impulse response length that is at least 2·N·M−5, where N is an excess-rate oversampling ratio of said apparatus and M is the number of processing branches.

14. An apparatus according to claim 1 , wherein the moving-average filter is comprised of cascaded moving-average filter stages having an impulse response length that is at least 4·N·M−5, where N is an excess-rate oversampling ratio of said apparatus and M is the number of processing branches.

15. An apparatus according to claim 1 , wherein the digital bandpass filter further includes an equalizer.

16. An apparatus according to claim 15 , wherein the equalizer has a single complex tap.

17. An apparatus according to claim 15 , wherein the equalizer has a single real tap.

18. An apparatus according to claim 15 , wherein the equalizer has plural complex taps.

19. An apparatus according to claim 15 , wherein the equalizer has plural real taps.

20. An apparatus according to claim 1 , wherein sine and cosine sequences are used by the quadrature frequency downconverter and the quadrature frequency upconverter for quadrature downconversion and upconversion, respectively, and are generated through direct digital synthesis using digital accumulators and sinusoid lookup.

21. An apparatus according to claim 1 , wherein sine and cosine sequences are used by the quadrature frequency downconverter and the quadrature frequency upconverter for quadrature downconversion and upconversion, respectively, and are generated using recursive structures.

22. An apparatus according to claim 1 , wherein sine and cosine sequences are used by the frequency downconverter and the frequency upconverter for quadrature downconversion and upconversion, respectively, and wherein at least one of an amplitude or phase of the sine and cosine sequences is adjustable.

23. An apparatus according to claim 1 , wherein sine and cosine sequences are used by the frequency downconverter and the frequency upconverter for quadrature downconversion and upconversion, respectively, and wherein the period of the sine and cosine sequences is adjustable.

24. An apparatus according to claim 1 , further comprising a configuration means for converting a first signal sample rate generated by the sampling/quantization circuit in at least one of the various processing branches to a second signal sample rate that is different than the first signal sample rate.

25. An apparatus according to claim 24 , wherein the configuration means includes at least one digital interpolator.

26. An apparatus according to claim 25 , wherein interpolation used by the at least one digital interpolator is at least second-order.

27. An apparatus according to claim 25 , wherein interpolation used by the at least one digital interpolator is first-order.

28. An apparatus according to claim 25 , wherein the at least one digital interpolator is implemented as a polyphase decomposition structure.

29. An apparatus according to claim 25 , wherein an interpolant used by the at least one digital interpolator is generated using a numerically-controlled oscillator.

30. An apparatus according to claim 1 , wherein a configuration means is provided to enable plural modes of operation, including: (i) a mode for operation as a single, wideband converter with high output data rate, and (ii) a mode for operation as plural, independent converters having an arbitrary mix of narrowband and wideband outputs at various sample rates.

31. An apparatus according to claim 30 , wherein the configuration means comprises an add-multiplex array.

32. An apparatus according to claim 30 , wherein the number of processing branches M is a power of two.

33. An apparatus according to claim 1 , wherein the plurality of processing branches includes at least 4 said processing branches, and in each of a plurality of said processing branches: the continuous-time quantization-noise-shaping circuit includes at least a second-order feedback filter, the sampling/quantization circuit samples at a frequency of at least 1 gigahertz (GHz), and the digital bandpass filter attenuates shaped quantization noise by at least 40 dB and introduces total aliasing distortion power limited to less than 40 dB below data converter signal level.

34. An apparatus according to claim 1 , wherein each of a plurality of the processing branches includes at least one quadrature downconverter that decreases, by a factor of at least two, a center frequency of the frequency band selected for said processing branch.

35. An apparatus according to claim 34 , wherein the digital bandpass filter includes at least one of a downconverter and an upconverter having at least one parameter that can be adjusted to compensate for at least one of amplitude or phase imbalance of the quadrature frequency downconverter.

36. An apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, comprising:

an input line for accepting an input signal that is continuous in time and continuously variable;

a plurality of processing branches coupled to the input line, each of said processing branches including: (a) a continuous-time quantization-noise-shaping circuit, (b) a multi-bit sampling/quantization circuit coupled to an output of the continuous-time quantization-noise-shaping circuit, (c) a nonlinear bit-mapping circuit coupled to an output of the multi-bit sampling/quantization circuit, (d) a digital bandpass filter coupled to an output of the nonlinear bit-mapping circuit, (e) a digital-to-analog converter (DAC) circuit coupled to the output of the multi-bit sampling/quantization circuit, and (f) a line coupling an output of the digital-to-analog converter circuit back into the continuous-time quantization-noise-shaping circuit; and

an adder coupled to outputs of the plurality of processing branches,

wherein a frequency band selected by the digital bandpass filter in each said processing branch corresponds to a minimum in a quantization noise transfer function for the continuous-time quantization-noise-shaping circuit in the same processing branch, and

wherein the nonlinear bit-mapping circuit in each of said processing branches performs a scaling operation, on a bit-by-bit basis, that matches imperfections in a binary scaling response of the digital-to-analog converter in the same processing branch.

37. An apparatus according to claim 36 , wherein the nonlinear bit-mapping circuit converts a digital input to a higher-precision digital output having other than perfect binary weighting.

38. An apparatus according to claim 36 , wherein the nonlinear bit-mapping circuit applies input-bit weighting factors to the digital input and at least one of the input-bit weighting factors applied by the nonlinear bit-mapping circuit is programmable.

39. An apparatus according to claim 38 , wherein the input-bit weighting factors are independently adjusted to minimize at least one of a mean absolute value or a variance of a residual quantization noise of the continuous-time quantization-noise-shaping circuit.

40. An apparatus according to claim 36 , wherein the digital-to-analog converter circuit operates in an unclocked mode.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2021
From: PAGNANELLI, CHRISTOPHER; SYNTROPY SYSTEMS, LLC
To: PAGNANELLI FAMILY TRUST
Reel/Frame 057998/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2021
From: SYNTROPY SYSTEMS, LLC
To: PAGNANELLI, CHRISTOPHER
Reel/Frame 055928/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2012
From: PAGNANELLI, CHRISTOPHER
To: SYNTROPY SYSTEMS, LLC
Reel/Frame 027631/0327 →
Continuity (15)
Continuation In Part 12985238 · Jan 5, 2011
Continuation In Part 12824171 · Jun 26, 2010
Continuation In Part 12985238
Continuation In Part 12985214 · Jan 5, 2011
Continuation In Part 13227668 · Sep 8, 2011
Provisional Application 61292428 · Jan 5, 2010
Provisional Application 61381055 · Sep 8, 2010
Provisional Application 61414413 · Nov 16, 2010
Provisional Application 61221009 · Jun 26, 2009
Provisional Application 61290817 · Dec 29, 2009
Provisional Application 61554918 · Nov 2, 2011
Provisional Application 61549739 · Oct 20, 2011
Provisional Application 61501284 · Jun 27, 2011
Provisional Application 61439733 · Feb 4, 2011
Related Publication 20120127009A1 · May 24, 2012