System and method for managing timing margin in a hierarchical integrated circuit design process
A system for, and method of, generating block timing constraints and a timing model. In one embodiment, the system includes a hierarchical modeling tool configured to: (1) generate a model file, (2) receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in the model file, (3) generate block implementation timing constraints employing the at least one timing environment margin and the at least one operational margin and (4) generate a block timing model employing the at least one abstracted view margin and the at least one operational margin.
1. A system for generating block timing constraints and a timing model, comprising:
a hierarchical modeling tool configured to:
receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in a model file,
generate block implementation timing constraints employing said at least one timing environment margin and said at least one operational margin, and
generate a block timing model employing said at least one abstracted view margin and said at least one operational margin.
2. The system as recited in claim 1 wherein at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin is specified block-wide.
3. The system as recited in claim 1 wherein at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin is specified on a per-pin basis.
4. The system as recited in claim 1 wherein at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin is specified as a fixed additive or subtractive value.
5. The system as recited in claim 1 wherein at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin is specified as a multiplier to existing constraint and timing arc values.
6. The system as recited in claim 1 wherein said at least one abstracted view margin is determined from correlation studies between a modeling method used in top-level implementation and a modeling method used in top-level signoff.
7. The system as recited in claim 1 wherein said at least one timing environment margin includes at least one of a top-level clock crosstalk margin and a top-level clock OCV margin.
8. The system as recited in claim 7 wherein said top-level clock crosstalk margin is applied in block-level timing constraints as source latencies on input clocks.
9. The system as recited in claim 1 wherein said at least one operational margin includes at least one of a block isolation margin and a block constraint margin.
10. A method of generating block timing constraints and a timing model, comprising:
receiving, using a computer, at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in a model file;
generating block implementation timing constraints employing said at least one timing environment margin and said at least one operational margin; and
generating a block timing model employing said at least one abstracted view margin and said at least one operational margin.
11. The method as recited in claim 10 further comprising specifying at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin block-wide.
12. The method as recited in claim 10 further comprising specifying at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin on a per-pin basis.
13. The method as recited in claim 10 further comprising specifying at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin as a fixed additive or subtractive value.
14. The method as recited in claim 10 further comprising specifying at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin as a multiplier to existing constraint and timing arc values.
15. The method as recited in claim 10 further comprising determining said at least one abstracted view margin from correlation studies between a modeling method used in top-level implementation and a modeling method used in top-level signoff.
16. The method as recited in claim 10 wherein said at least one timing environment margin includes at least one of a top-level clock crosstalk margin and a top-level clock OCV margin.
17. The method as recited in claim 16 further comprising applying said top-level clock crosstalk margin in block-level timing constraints as source latencies on input clocks.
18. The method as recited in claim 10 wherein said at least one operational margin includes at least one of a block isolation margin and a block constraint margin.
19. A non-transitory computer-readable storage medium containing program instructions for generating block timing constraints and a timing model, execution of said program instructions by one or more processors of a computer system causing said one or more processors to:
receive at least one abstracted view margin, at least one timing environment margin and at least one operational margin for inclusion in a model file;
generate block implementation timing constraints employing said at least one timing environment margin and said at least one operational margin; and
generate a block timing model employing said at least one abstracted view margin and said at least one operational margin.
20. The medium as recited in claim 19 wherein said one or more processors of said computer system cause said one or more processors to specify at least one of said at least one abstracted view margin, at least one timing environment margin and at least one operational margin one of block-wide and on a per-pin basis.