Power supply circuit for reduced wake-up time
View Patent ↗An electronic circuit includes a switchable circuit domain that operates in a RUN mode and a STANDBY mode and receives a supply current from a core power supply. A power regulator is connected between the core power supply and the switchable circuit domain to regulate the supply current provided to the switchable circuit domain when the electronic circuit is in the RUN mode. A capacitor is connected between the power regulator and ground and is charged by a refresh circuit when the electronic circuit is in the STANDBY mode. The refresh circuit maintains a voltage across the capacitor when the electronic circuit is in the standby mode, which reduces the time for the electronic circuit to transition from the STANDBY mode to the RUN mode.
1. A power supply circuit for providing a supply current to an electronic circuit, wherein the electronic circuit operates in a run mode and a standby mode and receives the supply current in the run mode, the power supply circuit comprising;
a power regulator, connected to a core power supply and the electronic circuit, for regulating the supply current provided to the electronic circuit when the electronic circuit is in the run mode;
a capacitor having a first terminal connected to the power regulator and a second terminal connected to ground, wherein the capacitor is charged to a predetermined voltage level by the core power supply when the electronic circuit transitions from the standby mode to the run mode;
a refresh circuit, comprising:
a first band gap voltage source for generating a voltage equivalent to the predetermined voltage level; and
a first buffer amplifier having an input terminal connected to the first band gap voltage source and an output terminal connected to an inverted input terminal of the first buffer amplifier and to the first terminal of the capacitor;
a first switch, connected between the refresh circuit and the first terminal of the capacitor, for connecting the refresh circuit to the capacitor when the electronic circuit is in the standby mode; and
a second switch, connected to the refresh circuit and the first switch, for receiving a power regulator control signal and an oscillator signal, and controlling the first switch;
wherein the refresh circuit maintains a voltage across the capacitor at about the predetermined voltage level when the electronic circuit is in the standby mode, thereby reducing time for the electronic circuit to transition from the standby mode to the run mode.
2. The power supply circuit of claim 1 , wherein the power regulator is enabled when the electronic circuit is in the run mode and disabled when the electronic circuit is in the standby mode, based on the power regulator control signal.
3. The power supply circuit of claim 1 , wherein the second switch further enables the first buffer amplifier when the electronic circuit is in the standby mode and disables the first buffer amplifier when the electronic circuit is in the run mode.
4. The power supply circuit of claim 1 , wherein the power regulator comprises:
a second band gap voltage source for generating the predetermined voltage; and
a second buffer amplifier having an input terminal connected to the first terminal of the capacitor and an inverted input terminal connected to the second band gap voltage source; and
a third switch connected to an output terminal of the second buffer amplifier, the core power supply and the electronic circuit, for conducting the supply current from the core power supply to the electronic circuit.
5. The power supply circuit of claim 4 , wherein the third switch is a metal-oxide semiconductor (MOS) switch.
6. The power supply circuit of claim 1 , wherein the first buffer amplifier is a unity gain amplifier.
7. An electronic circuit, comprising:
a circuit domain that operates in a run mode and a standby mode and receives a supply current from a core power supply when in the run mode;
a power regulator, connected to the core power supply and the circuit domain, for regulating the supply current provided to the circuit domain when the circuit domain is in the run mode;
a capacitor having a first terminal connected to the power regulator and a second terminal connected to ground, wherein the capacitor is charged to a predetermined voltage by the core power supply when the circuit domain transitions from the standby mode to the run mode;
a refresh circuit comprising:
a first band gap voltage source for generating a voltage equivalent to the predetermined voltage; and
a first buffer amplifier having an input terminal connected to the first band gap voltage source and an output terminal connected to an inverted input terminal of the first buffer amplifier and to the first terminal of the capacitor;
a first switch, connected between the refresh circuit and the first terminal of the capacitor, for connecting the refresh circuit to the capacitor when the circuit domain is in the standby mode; and
a second switch, connected to the refresh circuit and the first switch, for receiving a power regulator control signal and an oscillator signal, and controlling the second switch;
wherein the refresh circuit maintains a voltage across the capacitor at about the predetermined voltage when the circuit domain is in the standby mode, which allows the circuit domain to quickly transition from the standby mode to the run mode.
8. The electronic circuit of claim 7 , wherein the power regulator is enabled when the circuit domain is in the run mode and disabled when the circuit domain is in the standby mode, based on the power regulator control signal.
9. The electronic circuit of claim 7 , wherein the second switch further enables the first buffer amplifier when the circuit domain is in the standby mode and disables the first buffer amplifier when the circuit domain is in the run mode.
10. The electronic circuit of claim 7 , wherein the power regulator comprises:
a second band gap voltage source for generating the predetermined voltage; and
a second buffer amplifier having an input terminal connected to the first terminal of the capacitor and an inverted input terminal connected to the second band gap voltage source; and
a third switch connected to an output terminal of the second buffer amplifier, the core power supply and the circuit domain, for conducting the supply current from the core power supply to the circuit domain.
11. The electronic circuit of claim 10 , wherein the third switch is a metal-oxide semiconductor (MOS) switch.
12. The electronic circuit of claim 7 , wherein the first buffer amplifier is a unity gain amplifier.
13. An electronic circuit, comprising:
a circuit domain that operates in a run mode and a standby mode and receives a supply current from a core power supply when in the run mode;
a power regulator, connected to the core power supply and the circuit domain, for regulating the supply current provided to the circuit domain when the circuit domain is in the run mode;
a capacitor having a first terminal connected to the power regulator and a second terminal connected to ground, wherein the capacitor is charged to a predetermined voltage by the core power supply when the circuit domain transitions from the standby mode to the run mode;
a refresh circuit, comprising:
a first band gap voltage source for generating a voltage equivalent to the predetermined voltage;
a first buffer amplifier having an input terminal connected to the first band gap voltage source and an output terminal connected to an inverted input terminal of the first buffer amplifier and to the first terminal of the capacitor; and
wherein the refresh circuit maintains a voltage across the capacitor at about the predetermined voltage when the circuit domain is in the standby mode, thereby reducing time taken by the circuit domain to transition from the standby mode to the run mode, and
wherein the power regulator is enabled when the circuit domain is in the run mode and disabled when the circuit domain is in the standby mode, based on a power regulator control signal;
a first switch, connected between the refresh circuit and the first terminal of the capacitor, for connecting the refresh circuit to the capacitor when the circuit domain is in the standby mode; and
a second switch, connected to the refresh circuit and the first switch, for receiving the power regulator control signal and an oscillator signal and controlling the second switch,
wherein the power regulator comprises:
a second band gap voltage source for generating the predetermined voltage; and
a second buffer amplifier having an input terminal connected to the first terminal of the capacitor and an inverted input terminal connected to the second band gap voltage source; and
a third switch connected to an output terminal of the second buffer amplifier, the core power supply and the circuit domain, for conducting the supply current from the core power supply to the circuit domain.
14. The electronic circuit of claim 13 , wherein the second switch further enables the first buffer amplifier when the circuit domain is in the standby mode and disables the first buffer amplifier when the circuit domain is in the run mode.
15. The electronic circuit of claim 13 , wherein the third switch is a metal-oxide semiconductor (MOS) switch.
16. The electronic circuit of claim 13 , wherein the first buffer amplifier is a unity gain amplifier.