Method of forming a spin-transfer torque random access memory (STT-RAM) device
View Patent ↗A dual spin filter that minimizes spin-transfer magnetization switching current (Jc) while achieving a high dR/R in STT-RAM devices is disclosed. The bottom spin valve has a MgO tunnel barrier layer formed with a natural oxidation process to achieve low RA, a CoFe/Ru/CoFeB—CoFe pinned layer, and a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel (NCC) layer to minimize Jc 0 . The NCC layer may have be a composite wherein conductive M(Si) grains are magnetically coupled with adjacent ferromagnetic layers and are formed in an oxide, nitride, or oxynitride insulator matrix. The upper spin valve has a Cu spacer to lower the free layer damping constant. A high annealing temperature of 360° C. is used to increase the MR ratio above 100%. A Jc 0 of less than 1×10 6 A/cm 2 is expected based on quasistatic measurements of a MTJ with a similar MgO tunnel barrier and composite free layer.
1. A method of forming a STT-RAM device on a substrate wherein said substrate has a via stud formed in a first dielectric layer and an overlying bottom electrode layer that contacts said via stud and has a planar top surface, comprising:
(a) forming a dual-spin-filter (DSF) stack of layers on said planar top surface and above said via stud, said DSF stack of layers has a top surface and is comprised of:
(1) a seed layer;
(2) a first anti-ferromagnetic (AFM) layer.
(3) a first pinned layer comprised of CoFeB;
(4) a MgO tunnel barrier layer;
(5) a free layer having a FM1/NCC/FM2 configuration wherein said FM1 and FM2 layers are made of Fe, Co, Ni, FeB, or crystalline CoFeB and said NCC layer is a nanocurrent channel layer comprised of M(Si) grains in an oxide, nitride, or oxynitride matrix where M is a metal;
(6) a non-magnetic spacer;
(7) a second pinned layer;
(8) a second AFM layer; and
(9) a capping layer wherein the seed layer, first AFM layer, first pinned layer, MgO tunnel barrier, free layer, non-magnetic spacer, second pinned layer, second AFM layer, and capping layer are sequentially formed on the bottom electrode;
(b) annealing at a sufficient temperature to form a crystalline MgO layer and crystalline CoFeB layers;
(c) patterning said DSF stack of layers and the bottom electrode layer to form a DSF structure and a bottom electrode above said via stud, said DSF structure has a top surface and sidewalls and an elliptical shape or another rounded shape in a plane parallel to the top surface of the bottom electrode;
(d) depositing a second dielectric layer on the first dielectric layer and on the DSF structure;
(e) planarizing the second dielectric layer such that the second dielectric layer becomes coplanar with the capping layer; and
(f) forming a bit line on the second dielectric layer and on the capping layer.
2. The method of claim 1 wherein the MgO tunnel barrier layer is formed by depositing a first Mg layer on the first pinned layer, performing a natural oxidation of the first Mg layer to form a MgO layer, and then depositing a second Mg layer on the MgO layer.
3. The method of claim 1 wherein the annealing is performed at a temperature of about 350° C. to 360° C. for about 1 to 5 hours.
4. The method of claim 1 wherein the bottom electrode is comprised of Ta and has the same shape as the stack of layers.
5. The method of claim 1 wherein the first pinned layer has a configuration represented by CoFe/Ru/CoFeB—CoFe or CoFe/Ru/CoFeB and the second pinned layer is made of CoFe.
6. The method of claim 1 wherein the NCC layer has a FeSiO composition and a thickness from about 8 to 15 Angstroms.
7. The method of claim 1 wherein the CoFeB layers have a Co 40 Fe 40 B 20 composition.
8. The method of claim 1 wherein the capping layer is comprised of Ru, Ru/Ta, or Ru/Ta/Ru.
9. The method of claim 1 wherein the NCC layer is comprised of FeSiO and is formed by sputtering a target comprised of Fe 25 (SiO 2 ) 75 .
10. The method of claim 1 wherein the non-magnetic spacer is comprised of Cu.
11. The method of claim 1 further comprised of forming a Ta hard mask on the capping layer before annealing the DSF stack of layers.
12. The method of claim 1 wherein the FM1 and FM2 layers have a FeB composition represented by FeB x where x is from 0 to about 5 atomic %.
13. The method of claim 1 wherein the FM1 layer has a thickness greater than or equal to a thickness of the FM2 layer.