Data administration unit, data access unit, network element, network, and method for updating a data structure
View Patent ↗A data administration unit for updating a first data structure in a first memory may comprise a second memory, a data structure generator for setting up a second data structure in the second memory, a pointer generator for setting at least one of a dynamic change indicator and a pointer in the first data structure, a waiting unit for waiting for a finalization of a data access of a data access unit, and a data structure over-writer for overwriting the first data structure using data of the second data structure. An data access unit for accessing a first data structure in a first memory may comprise a data access driver, a first synchronization signal evaluator for reception and evaluation of a first synchronization signal, and a synchronization approval signal generator for generation and submission of a first synchronization signal.
1. A network element comprising:
a first memory;
a second memory;
a data administration circuit to update a first data structure stored at the first memory by over-writing, the data administration circuit comprising:
a data structure generator configured to set up a second data structure in the second memory,
a pointer generator configured to set at least one of a dynamic change indicator and a pointer in the first data structure, wherein the pointer points to the second data structure,
a waiting unit configured to wait for a finalization of a data access of a data access circuit,
a first synchronization signal generator configured to generate and submit a first synchronization signal to the data access circuit,
a synchronization approval signal receiver configured to receive a synchronization approval signal from the data access circuit, and
a data structure over-writer configured to overwrite the first data structure using data of the second data structure; and
the data access circuit, distinct from the data administration circuit, to access the first data structure, the data access circuit comprising:
a first synchronization signal evaluator configured to receive and evaluate the first synchronization signal, and
a synchronization approval signal generator configured to generate and submit the synchronization approval signal, the synchronization approval signal providing a temporal synchronization between an overwrite of the first data structure performed by the data administration circuit and an access of the first data structure performed by the data access circuit.
2. The network element according to claim 1 , wherein the data access circuit comprises a data access driver.
3. The network element according to claim 1 , the data administration circuit further comprising a second synchronization signal generator configured to generate and submit a second synchronization signal to the data access circuit.
4. The network element according to claim 1 , the data access circuit further comprising a second synchronization signal evaluator configured to receive and evaluate a second synchronization signal.
5. The network element according to claim 1 , wherein the data access circuit comprises a marker for tagging data packets allocated last.
6. The network element according to claim 1 , wherein the data access circuit is configured to access a data packet after receiving the first synchronization signal.
7. The network element according to claim 1 , wherein the pointer generator sets both the dynamic change indicator and the pointer in the first data structure and the data structure over-writer overwrites the dynamic change indicator and the pointer with data of the second data structure.
8. A method for updating a first data structure in a first memory of a network element by over-writing, the method comprising:
setting up a second data structure in a second memory of the network element with a data administration circuit of the network element;
setting a pointer in the first data structure, wherein the pointer points to the second data structure;
generating a first synchronization signal by the data administration circuit;
receiving the first synchronization signal at a data access circuit of the network element;
waiting for a finalization of a data access of the data access circuit on the first data structure in the first memory;
generating a synchronization approval signal by the data access circuit;
submitting the synchronization approval signal to the data administration circuit after finalization of the data access, the synchronization approval signal indicative of a temporal synchronization between the data access by the data access circuit and an over-writing of the first data structure by the data administration circuit; and
over-writing the first data structure in the first memory by the data administration circuit using data of the second data structure.
9. The method according to claim 8 , wherein the data access circuit evaluates the first data structure starting with a begin of the first data structure.
10. The method according to claim 9 , wherein the data access circuit continues the evaluation with the second data structure stored in the second memory, when the data access driver has recognized the pointer in the first data structure.
11. The method according to claim 8 , wherein the data access circuit, after reception of the first synchronization signal, tags a data packet allocated last.
12. The method according to claim 8 , further comprising transmitting the first synchronization signal from the data administration circuit to the data access circuit prior to submission of the synchronization approval signal to the data administration circuit.
13. The method according to claim 12 further comprising transmitting a second synchronization signal from the data administration circuit to the data access circuit subsequent to submission of the synchronization approval signal to the data administration circuit.
14. A network element comprising:
a first memory;
a second memory;
a data administration circuit configured to update a first data structure stored at the first memory by over-writing, the data administration circuit comprising:
a data structure generator configured to set up a second data structure in the second memory,
a pointer generator configured to set a pointer in the first data structure, wherein the pointer points to the second data structure,
a waiting unit configured to wait for a finalization of a data access of a data access circuit,
a first synchronization signal generator configured to generate and submit a first synchronization signal to the data access circuit,
a synchronization approval signal receiver configured to receive a synchronization approval signal from the data access circuit, the synchronization approval signal providing a temporal synchronization between an overwrite of the first data structure performed by the data administration circuit and an access of the first data structure performed by the data access circuit, and
a data structure over-writer configured to overwrite the first data structure using data of the second data structure; and
the data access circuit, distinct from the data administration circuit, configured to access the first data structure.
15. The network element according to claim 14 , wherein the data access circuit comprises:
a data access driver,
a first synchronization signal evaluator configured to receive and evaluate the first synchronization signal, and
a synchronization approval signal generator configured to generate and submit the synchronization approval signal.
16. The network element according to claim 14 , the data administration circuit further comprising a second synchronization signal generator configured to generate and submit a second synchronization signal to the data access circuit.
17. The network element according to claim 14 , the data access circuit further comprising a second synchronization signal evaluator configured to receive and evaluate a second synchronization signal.
18. The network element according to claim 14 , wherein the data access circuit comprises a marker for tagging data packets allocated last.