Signal processing system, integrated circuit comprising buffer control logic and method therefor
View Patent ↗A signal processing system comprising buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element. Upon receipt of fetched information to be buffered, the buffer control logic is arranged to categorize the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow, and to prioritize respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.
1. A signal processing system comprising:
buffer control logic arranged to allocate a plurality of buffers for the storage of information fetched from at least one memory element, wherein, upon receipt of fetched information to be buffered, the buffer control logic is arranged to: categorise the information to be buffered according to at least one of: a first category associated with sequential flow and a second category associated with change of flow; and the buffer control logic is arranged to prioritise respective buffers from the plurality of buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.
2. The signal processing system of claim 1 wherein the buffer control logic is arranged to prioritise buffers for the storage of information to be buffered if neither of a vacant buffer nor a buffer storing unused information is available.
3. The signal processing system of claim 1 wherein the buffer control logic is further arranged to maintain a minimum number of most recently allocated sequential flow information buffers.
4. The signal processing system of claim 3 wherein the buffer control logic is further arranged to track branch spans for change of flow fetches, and to adjust the minimum number value for the most recently allocated sequential flow information buffers in accordance with the tracked branch spans.
5. The signal processing system of claim 3 wherein the minimum number value for the most recently allocated sequential flow information buffers is configurable by software executed on a master device of the signal processing system.
6. The signal processing system of claim 1 wherein, upon receipt of fetched information relating to a change of flow, the buffer control logic is arranged to categorise information to be buffered according to a change of flow span for the information to be buffered.
7. The signal processing system of claim 6 wherein the buffer control logic is arranged to determine a change of flow span for the information to be buffered, and if the determined change of flow span is less than a threshold span length to categorise the information as sequential flow information.
8. The signal processing system of claim 1 wherein the buffer control logic is arranged, upon determining an appropriate category of stored information to be replaced, to allocate a buffer storing the least recently used information of the appropriate category.
9. An integrated circuit comprising the signal processing system of claim 1 .
10. The signal processing system of claim 2 wherein the buffer control logic is further arranged to maintain a minimum number of most recently allocated sequential flow information buffers.
11. The signal processing system of claim 2 wherein, upon receipt of fetched information relating to a change of flow, the buffer control logic is arranged to categorise information to be buffered according to a change of flow span for the information to be buffered.
12. The signal processing system of claim 3 wherein, upon receipt of fetched information relating to a change of flow, the buffer control logic is arranged to categorise information to be buffered according to a change of flow span for the information to be buffered.
13. The signal processing system of claim 6 wherein the buffer control logic is arranged, upon determining an appropriate category of stored information to be replaced, to allocate a buffer storing the least recently used information of the appropriate category.
14. The signal processing system of claim 2 wherein the buffer control logic is arranged, upon determining an appropriate category of stored information to be replaced, to allocate a buffer storing the least recently used information of the appropriate category.
15. The signal processing system of claim 3 wherein the buffer control logic is arranged, upon determining an appropriate category of stored information to be replaced, to allocate a buffer storing the least recently used information of the appropriate category.
16. The signal processing system of claim 1 wherein the sequential flow is an information flow with memory access requests that relate to sequential addresses for information within the at least one memory element.
17. The signal processing system of claim 1 wherein the change of flow is a forward branch that includes accessed address jumps beyond a current buffer length.
18. A method for buffering information, the method comprising:
receiving information to be buffered;
categorising the information to be buffered according to at least one of a first category associated with sequential flow and a second category associated with change of flow; and
prioritising buffers storing information relating to the first category associated with sequential flow ahead of buffers storing information relating to the second category associated with change of flow when allocating a buffer for the storage of the fetched information to be buffered.
19. The method of claim 18 wherein the sequential flow is an information flow with memory access requests that relate to sequential addresses for information within the at least one memory element.
20. The method of claim 18 wherein the change of flow is a forward branch that includes accessed address jumps beyond a current buffer length.