Reference generator with programmable M and B parameters and methods of use
View Patent ↗A reference generator with programmable m and b parameters and methods of use are provided. A circuit includes a first generator operable to generate a first voltage including a fraction of a supply voltage. The circuit further includes a second generator operable to generate a second voltage. The circuit further includes a mixer and buffer circuit operable to output a reference voltage including a sum of the first and second voltages.
1. A circuit comprising:
a first generator operable to generate a first voltage comprising a fraction of a supply voltage;
a second generator operable to generate a second voltage; and
a mixer and buffer circuit operable to output a reference voltage comprising a sum of the first and second voltages, and output a buffered low reference voltage and a buffered high reference voltage based on the sum of the first and second voltages.
2. The circuit of claim 1 , wherein the second voltage is independent of the supply voltage.
3. The circuit of claim 1 , wherein the mixer and buffer circuit is further operable to generate and output the buffered high reference voltage comprising a sum of the reference voltage and an offset voltage.
4. The circuit of claim 1 , wherein the first and second voltages are adjustable by respective digital control words.
5. The circuit of claim 1 , wherein the first generator comprises an operational amplifier comprising a negative feedback, and the operational amplifier is operable to buffer the first voltage.
6. The circuit of claim 5 , wherein the first generator further comprises a selectable resistor circuit operable to input the first voltage into the negative feedback of the operational amplifier based on digital control words.
7. The circuit of claim 5 , wherein the first generator further comprises a current supply circuit operable to increase linearity of a current based on the first voltage.
8. The circuit of claim 1 , wherein the second generator comprises an operational amplifier comprising a negative feedback, and the operational amplifier is operable to buffer the second voltage.
9. The circuit of claim 8 , wherein the second generator further comprises a selectable resistor circuit operable to input the second voltage into the negative feedback of the operational amplifier based on digital control words.
10. The circuit of claim 8 , wherein the second generator further comprises a current supply circuit operable to increase linearity of a current based on the second voltage.
11. A circuit of a dynamic random access memory (DRAM), comprising:
a reference generator operable to generate a reference voltage comprising a fraction of a supply voltage that is added to a direct current (DC) voltage, the reference voltage being centered between signal voltages of 1 and 0 data types of the DRAM; and
a sense amplifier operable to sense the 1 and 0 data types based on differences between the reference voltage and the respective signal voltages.
12. The circuit of claim 11 , wherein both the fraction of the supply voltage and the DC voltage are adjustable by respective digital control words.
13. The circuit of claim 11 , further comprising a plurality of DRAM cells coupled to bit-lines operable to provide the signal voltages to the sense amplifier.
14. The circuit of claim 11 , further comprising a reference cell coupled to the reference generator, the reference cell being operable to provide the reference voltage to the sense amplifier.
15. The circuit of claim 11 , wherein the reference generator comprises a mixer and buffer circuit operable to:
add the fraction of the supply voltage to the DC voltage to generate the reference voltage; and
output the reference voltage to the sense amplifier.
16. The circuit of claim 15 , wherein the mixer and buffer circuit comprises an operational amplifier comprising a negative feedback, and the operational amplifier is operable to buffer the reference voltage.
17. The circuit of claim 15 , wherein the mixer and buffer circuit is further operable to generate and output a high reference voltage comprising a sum of the reference voltage and an offset voltage.
18. A design structure tangibly embodied in a machine readable memory for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
a first generator operable to generate a first voltage comprising a fraction of a supply voltage;
a second generator operable to generate a second voltage; and
a mixer and buffer circuit operable to output a reference voltage comprising a sum of the first and second voltages, and output a buffered low reference voltage and a buffered high reference voltage based on the sum of the first and second voltages.
19. The design structure of claim 18 , wherein the design structure comprises a netlist.
20. The design structure of claim 18 , wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
21. The design structure of claim 18 , wherein the design structure resides in a programmable gate array.
22. A method of optimizing semiconductor device yield and performance, comprising:
defining signal voltages of 1 and 0 data types in a semiconductor device; and
interpolating a best fit line for a reference voltage to be used by the semiconductor device, the reference voltage comprising a fraction of a supply voltage that is added to a direct current (DC) voltage, and the best fit line being centered between the signal voltages and comprising a slope and an intercept.
23. The method of claim 22 , further comprising programming the slope and the intercept into a reference generator of the semiconductor device via respective digital control words.
24. A method in a computer-aided design system for generating a functional design model of a reference generator with programmable m and b parameters, the method comprising:
generating a functional representation of a first generator operable to generate a first voltage comprising a fraction of a supply voltage;
generating a functional representation of a second generator operable to generate a second voltage;
generating a functional representation of a mixer and buffer circuit operable to output a reference voltage comprising a sum of the first and second voltages, the reference voltage being centered between signal voltages of 1 and 0 data types of a dynamic random access memory (DRAM); and
generating a functional representation of a sense amplifier operable to sense the 1 and 0 data types based on differences between the reference voltage and the respective signal voltages.
25. The method of claim 24 , wherein:
the second voltage is independent of the supply voltage;
the mixer and buffer circuit is further operable to generate and output a high reference voltage comprising a sum of the reference voltage and an offset voltage; and
the first and second voltages are adjustable by respective digital control words.
26. The method of claim 24 , wherein the first voltage is a slope of the reference voltage with respect to a supply voltage; and
the second voltage is a predetermined intercept of the reference voltage at the supply voltage of 0.
27. The method of claim 1 , wherein the first generator and the second generator each include an operational amplifier, a selectable resistor circuit, and a current supply circuit, and the first generator includes a voltage divider circuit.