IP Library Granted Patent US 8,487,805
Granted Patent B1
US 8,487,805 · App. 13/403,945 · Granted Jul 16, 2013

Successive approximation analog-to-digital converter

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Quick Facts
Patent No.
US 8,487,805
App. No.
13/403,945
Granted
Jul 16, 2013
Kind
B1
Abstract

An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.

Claims (29)

1. A system for converting an analog input signal to a digital output signal in one or more analog-to-digital conversion cycles, comprising:

a sample-and-hold circuit for sampling the analog input signal to obtain a first analog sample in a sampling cycle;

a processor for determining a count of least significant bits of the digital output signal that alternate between the first analog sample and a second analog sample of the analog input signal based on a frequency of the analog input signal and a predetermined bit-length of the digital output signal; and

an analog-to-digital converter (ADC), connected to the sample and hold circuit and the processor, for converting the first analog sample to the digital output signal using a successive approximation algorithm, wherein the ADC executes the successive approximation algorithm for a count equal to the count of the least significant bits that alternate between the first and second analog samples.

2. The system of claim 1 , wherein the second analog sample is sampled in a previous sampling cycle.

3. The system of claim 1 , further comprising:

a memory, connected to the processor, for storing a look-up table comprising a mapping of a plurality of signal bandwidths of the analog input signal and the corresponding count of least significant bits that alternate between the first and second analog samples of the analog input signal.

4. The system of claim 1 , wherein the processor further determines a first analog-to-digital conversion cycle.

5. The system of claim 4 , wherein the ADC further executes the successive approximation algorithm for a count equal to the predetermined bit-length of the digital output signal in the first analog-to-digital conversion cycle.

6. The system of claim 4 , wherein a bandwidth of the analog input signal is less than half of a sampling frequency.

7. The system of claim 4 , wherein a frequency band of the analog input signal is provided by a user.

8. A method for converting an analog input signal to a digital output signal in one or more analog-to-digital conversion cycles, comprising:

sampling the analog input signal to obtain a first analog sample in a sampling cycle;

determining a count of least significant bits of the digital output signal that alter between the first analog sample and a second analog sample of the analog input signal based on a frequency of the analog input signal and a predetermined bit-length of the digital output signal, wherein the second analog sample is sampled in a previous sampling cycle; and

converting the first analog sample to the digital output signal using a successive approximation algorithm, wherein the successive approximation algorithm is executed for a count equal to the count of the least significant bits that alter between the first and second analog samples.

9. The method of claim 8 , wherein converting the first analog sample to the digital output signal further comprises:

comparing a magnitude of the first analog sample with a magnitude of a comparison voltage;

modifying the magnitude of the comparison voltage based on the magnitude of the first analog sample, wherein modifying the comparison voltage comprises at least one of an increasing and decreasing the magnitude of the comparison voltage by a predetermined value; and

generating the digital output signal corresponding to the first analog sample.

10. The method of claim 8 , wherein the successive approximation algorithm is executed for a count equal to the predetermined bit-length of the digital output signal in a first analog-to-digital conversion cycle.

11. The method of claim 8 , wherein a frequency band of the analog input signal is input by a user.

12. A method for converting an analog input signal to a digital output signal in one or more analog-to-digital conversion cycles, comprising:

sampling the analog input signal to obtain a first analog sample in a sampling cycle;

determining a count of least significant bits of the digital output signal that alter between the first analog sample and a second analog sample of the analog input signal based on a frequency of the analog input signal and a predetermined bit-length of the digital output signal, wherein the second analog sample is sampled in a previous sampling cycle; and

comparing a magnitude of the first analog sample with a magnitude of a comparison voltage;

modifying the magnitude of the comparison voltage based on the magnitude of the first analog sample, wherein modifying the comparison voltage comprises at least one of an increasing and decreasing the magnitude of the comparison voltage by a predetermined value; and

generating the digital output signal corresponding to the first analog sample by executing a successive approximation algorithm for a count equal to the count of the least significant bits that alter between the first and second analog samples.

13. The method of claim 12 , wherein the successive approximation algorithm is executed for a count equal to the predetermined bit-length of the digital output signal in a first analog-to-digital conversion cycle.

14. The method of claim 12 , wherein a frequency band of the analog input signal is input by a user.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0521 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0455 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0476 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2012
From: GUPTA, SUNNY; ABHISHEK, KUMAR; KAMAL, KUSHAL; SINHA, SAMAKSH
To: FREESCALE SEMICONDUCTOR, INC.
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