Package-on-package assembly with wire bond vias
View Patent ↗A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
1. A microelectronic package comprising:
a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;
at least one microelectronic element overlying the first surface within the first region;
electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds, each defining a base joined to a respective one of the conductive elements, and each wire bond having a second portion extending in a direction of a length of the respective wire bond away from the respective base, the second portion extending upwardly relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends remote from the substrate and remote from the bases, wherein at least one of the wire bonds has an axis defined between the end and the base thereof and coincident with a side surface thereof, wherein the at least one of the wire bonds in its entirety is positioned on one side of the axis thereof, wherein the end of the at least one of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion of the at least one of the wire bonds immediately adjacent the tip but not in a direction opposite to the at least one direction extending beyond the cylindrical portion, in which the tip has a centroid that is offset in a radial direction from an axis of the cylindrical portion of the wire bond; and
a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.
2. The microelectronic package as set forth in claim 1 , wherein the angle is between 45° and 90°.
3. The microelectronic package as set forth in claim 1 , wherein a first one of the wire bonds is adapted for carrying a first signal electric potential and a second one of the wire bonds is adapted for simultaneously carrying a second signal electric potential different from the first signal electric potential.
4. The microelectronic package as set forth in claim 1 , wherein each wire bond has an edge surface extending between the base and at least the end thereof, wherein the unencapsulated portions of the wire bonds are defined by the ends of the wire bonds and portions of edge surfaces adjacent the ends that are uncovered by the encapsulation layer.
5. The microelectronic package as set forth in claim 1 , wherein the tapered tips on which at least some of the ends are defined are tapered in multiple directions.
6. The microelectronic package as set forth in claim 1 , wherein the tips have bonding tool marks thereon.
7. The microelectronic package as set forth in claim 1 , further comprising an oxidation protection layer contacting at least some of the unencapsulated portions of the wire bonds.
8. The microelectronic package as set forth in claim 1 , wherein at least some of the wire bonds have a core of a primary metal and a metallic finish including a second metal different from the primary metal overlying the primary metal.
9. The microelectronic package as set forth in claim 8 , wherein the metallic finish includes palladium.
10. The microelectronic package as set forth in claim 1 , wherein at least some of the wire bonds are formed of a primary metal, with a layer of nickel overlying the primary metal and a layer of gold or silver overlying the layer of nickel.
11. The microelectronic package as set forth in claim 10 , wherein the primary metal is one of gold or copper.
12. The microelectronic package as set forth in claim 1 , wherein the conductive elements are first conductive elements, the microelectronic package further comprising a plurality of second conductive elements electrically connected to the unencapsulated portions of the wire bonds, wherein the second conductive elements do not contact the first conductive elements.
13. The microelectronic package as set forth in claim 12 , wherein the second conductive elements include a monolithic metal layer consisting essentially of a single metal.
14. The microelectronic package as set forth in claim 13 , wherein the single metal is one of: nickel, gold, copper, palladium or silver.
15. The microelectronic package as set forth in claim 12 , wherein the second conductive elements include a conductive paste contacting the unencapsulated portions of the wire bonds.
16. The microelectronic package as set forth in claim 1 , wherein an end of at least one of the wire bonds is displaced in a direction parallel to the first surface of the substrate from its base by at least a distance equal to one of: a minimum pitch between adjacent conductive elements of the plurality of conductive elements, and 100 microns.
17. The microelectronic package as set forth in claim 16 , wherein at least one of the wire bonds includes at least one bend between the base thereof and the unencapsulated portion thereof.
18. The microelectronic package as set forth in claim 17 , wherein the bend of the at least one wire bond is remote from the base thereof and remote from the unencapsulated portion thereof.
19. The microelectronic package as set forth in claim 17 , wherein the unencapsulated portion of the at least one wire bond overlies a major surface of the microelectronic element.
20. The microelectronic package as set forth in claim 1 , wherein the bases of the wire bonds are disposed at positions in a first pattern having a first minimum pitch between respective adjacent bases of the plurality of wire bonds, and the unencapsulated portions of the wire bonds are disposed at positions in a second pattern having a second minimum pitch between respective adjacent unencapsulated portions of wire bonds of the plurality of wire bonds, the second minimum pitch being greater than the first pitch.
21. The microelectronic package as set forth in claim 1 , wherein the at least one microelectronic element includes first and second microelectronic elements overlying the first surface within the first region, and wherein at least some of the conductive elements are connected with the first microelectronic element, wherein at least some conductive elements are connected with the second microelectronic element, and wherein the first microelectronic element and the second microelectronic elements are electrically connected with one another within the microelectronic package.
22. The microelectronic package as set forth in claim 1 , wherein at least one of the first conductive elements has at least two wire bonds joined thereto.
23. A microelectronic assembly, comprising:
a first microelectronic package according to claim 1
a second microelectronic package including a second microelectronic element and terminals electrically connected to the second microelectronic element and exposed at a surface of the second microelectronic package; and
a plurality of conductive protrusions electrically connecting at least some of the unencapsulated portions of the wire bonds with respective ones of the terminals.
24. The microelectronic assembly as set forth in claim 23 , wherein the encapsulation layer of the first microelectronic package includes a major surface and an alignment surface sloping upwardly away from the major surface, at least one unencapsulated portion of the wire bond being positioned on the major surface and the alignment surface extending to a location proximate the major surface and proximate the at least one unencapsulated portion of the wire bond such that a conductive protrusion connecting the at least one unencapsulated portion of the wire bond contacts the alignment surface.
25. The microelectronic assembly as set forth in claim 23 , further including an underfill disposed within a space defined between confronting surfaces of the first microelectronic package and the second microelectronic package and between respective adjacent conductive protrusions of the plurality of conductive protrusions.
26. The microelectronic assembly as set forth in claim 1 , wherein the wire bonds define edge surfaces having portions defined along the bases of the wire bonds such that the bases are bonded to the respective ones of the conductive elements with the edge surfaces extending along the conductive elements.
27. The microelectronic assembly as set forth in claim 26 , wherein the second portions of the wire bonds extend upwardly relative to the at least one surface of the substrate at an angle between 25° and 90° relative to the bases.
28. The microelectronic assembly as set forth in claim 26 , wherein the portions of the edge surfaces along the bases are wedge bonded or stitch bonded to the respective ones of the conductive elements.
29. A microelectronic package comprising:
a substrate having a first region and a second region, the substrate having a first surface and a second surface remote from the first surface;
at least one microelectronic element overlying the first surface within the first region;
electrically conductive elements exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds, each defining a base joined to a respective one of the conductive elements, and each wire bond having a second portion extending in a direction of a length of the respective wire bond away from the respective base, the second portion extending upwardly relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends remote from the substrate and remote from the bases, wherein each of at least some of the wire bonds has an axis defined between the end and the base thereof and coincident with a side surface thereof, wherein the each of the at least some of the wire bonds in its entirety is positioned on one side of the axis thereof, wherein the ends of the at least some of the wire bonds are defined on tips that are tapered in at least one direction extending beyond cylindrical portions respectively of the at least some of the wire bonds immediately adjacent the tips but not in a direction opposite to the at least one direction extending beyond the cylindrical portions, in which the ends have bonding tool marks thereon; and
a dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, the encapsulation layer overlying at least the second region of the substrate, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.