IP Library Assignment 069087/0330
Patent Assignment
Reel/Frame 069087/0330

Change of Name

Recorded: 2024-10-02 Pages: 6
Assignor
INVENSAS LLC
Executed: 2022-08-15
Assignee
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
3025 ORCHARD PARKWAY, SAN JOSE, CALIFORNIA, 95134
Covered Properties (68)
Microelectronic Element with Bond Elements to Encapsulation Surface
Application: 15/286,086 →
Publication: US US20170025390A1
Multichip Modules and Methods of Fabrication
Patent: 9,666,559 →
Application: 14/809,036 →
Publication: US US20160071818A1
Multichip modules and methods of fabrication
Application: 15/584,961 →
Publication: US US20170236794A1
Multichip Modules and Methods of Fabrication
Application: 16/196,313 →
Publication: US US20190088607A1
Embedded wire bond wires
Application: 14/993,586 →
Publication: US US20170103968A1
Nanoscale Interconnect Array for Stacked Dies
Application: 15/147,807 →
Publication: US US20170323867A1
Nanoscale Interconnect Array for Stacked Dies
Application: 16/378,921 →
Publication: US US20190237437A1
Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
Patent: 9,984,992 →
Application: 14/997,774 →
Publication: US US20170194281A1
Embedded Wire Bond Wires for Vertical Integration with Separate Surface Mount and Wire Bond Mounting Surfaces
Application: 15/959,619 →
Publication: US US20180240773A1
Embedded Vialess Bridges
Patent: 9,852,994 →
Application: 15/354,061 →
Publication: US US20170170121A1
Embedded Vialess Bridges
Application: 15/845,333 →
Publication: US US20180108612A1
Embedded Vialess Bridges
Application: 16/136,635 →
Publication: US US20190019754A1
Correction Die for Wafer/Die Stack
Application: 15/057,083 →
Publication: US US20170250161A1
Correction Die for Wafer/Die Stack
Application: 16/823,391 →
Publication: US US20200219852A1
Correction Die for Wafer/Die Stack
Application: 18/107,823 →
Publication: US US20230268320A1
System and Method for Providing 3D Wafer Assembly with Known-Good-Dies
Application: 15/834,658 →
Publication: US US20180096973A1
Stacked Transmission Line
Application: 15/192,549 →
Publication: US US20170374734A1
Stacked Transmission Line
Application: 16/172,271 →
Publication: US US20190069392A1
Warpage Balancing in Thin Packages
Patent: 9,972,582 →
Application: 15/670,382 →
Publication: US US20180040572A1
Warpage Balancing In Thin Packages
Application: 15/977,905 →
Publication: US US20180261556A1
Wire Bonding Method and Apparatus for Electromagnetic Interference Shielding
Patent: 9,935,075 →
Application: 15/237,936 →
Publication: US US20180033764A1
Wire Bonding Method and Apparatus for Electromagnetic Interference Shielding
Application: 15/914,617 →
Publication: US US20180197834A1
Wire Bonding Method and Apparatus for Electromagnetic Interference Shielding
Application: 16/833,445 →
Publication: US US20200227360A1
Deformable Electrical Contacts With Conformable Target Pads
Application: 15/980,894 →
Publication: US US20180359855A1
Remote Optical Engine for Virtual Reality or Augmented Reality Headsets
Application: 17/019,080 →
Publication: US US20200409157A1
Systems and Methods for Flash Stacking
Application: 15/993,271 →
Systems and Methods for Flash Stacking
Application: 16/368,219 →
Publication: US US20190371765A1
Systems and Methods for Flash Stacking
Application: 16/814,175 →
Publication: US US20200212013A1
Systems and Methods for Flash Stacking
Application: 17/217,749 →
Publication: US US20210225811A1
Connecting Multiple Chips Using an Interconnect Device
Application: 16/905,766 →
Publication: US US20200402913A1
Network On Layer Enabled Architectures
Application: 16/678,342 →
Publication: US US20200388592A1
Network On Layer Enabled Architectures
Application: 17/577,944 →
Publication: US US20220139883A1
Active Bridging Apparatus
Application: 16/868,701 →
Publication: US US20210351159A1
Symbiotic Network On Layers
Application: 16/842,199 →
Publication: US US20200387471A1
Ultrathin layer for forming a capacitive interface between joined Integrated Circuit Components
Application: 15/247,705 →
Publication: US US20170092620A1
Ultrathin Layer for Forming a Capacitive Interface Between Joined Integrated Circuit Component
Application: 16/020,654 →
Publication: US US20180366446A1
Capacitive Coupling in a Direct-Bonded Interface for Microelectronic Devices
Application: 16/212,248 →
Publication: US US20190115323A1
Capacitive Coupling in a Direct-Bonded Interface for Microelectronic Devices
Application: 17/074,401 →
Publication: US US20210035954A1
Capacitive Coupling in a Direct-Bonded Interface for Microelectronic Devices
Application: 17/959,585 →
Publication: US US20230040454A1
Multiple Plated via Arrays of Different Wire Heights on a Same Substrate
Patent: 49,987 →
Application: 17/725,442 →
Semiconductor Chip Package with Post Electrodes
Patent: 8,110,911 →
Application: 12/864,125 →
Publication: US US20100295178A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 9,105,483 →
Application: 13/404,408 →
Publication: US US20130093087A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 8,404,520 →
Application: 13/404,458 →
Publication: US US20130095610A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 8,836,136 →
Application: 13/405,108 →
Publication: US US20130093088A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 9,041,227 →
Application: 13/795,811 →
Publication: US US20130200533A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 9,252,122 →
Application: 13/966,636 →
Publication: US US20130328219A1
Package-On-Package Assembly with Wire Bond Vias
Patent: 9,761,558 →
Application: 14/718,719 →
Publication: US US20150255424A1
Package-On-Package Assembly with Wire Bond Vias
Application: 15/699,288 →
Publication: US US20180026007A1
Package-on-package Assembly With Wire Bond Vias
Application: 16/999,601 →
Publication: US US20210035948A1
Package-On-Package Assembly with Wire Bond Vias
Application: 17/512,123 →
Publication: US US20220165703A1
Package-On-Package Assembly with Wire Bond Vias
Application: 18/221,171 →
Publication: US US20240055393A1
Fine Pitch Bva Using Reconstituted Wafer with Area Array Accessible for Testing
Patent: 9,583,411 →
Application: 14/157,790 →
Publication: US US20150206815A1
Fine Pitch Bva Using Reconstituted Wafer with Area Array Accessible for Testing
Patent: 9,837,330 →
Application: 15/422,887 →
Publication: US US20170148696A1
Fine Pitch Bva Using Reconstituted Wafer with Area Array Accessible for Testing
Application: 15/827,550 →
Publication: US US20180082916A1
Fine Pitch Bva Using Reconstituted Wafer With Area Array Accessible For Testing
Application: 16/734,758 →
Publication: US US20200144144A1
THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON
Application: 15/157,197 →
Publication: US US20160343613A1
THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON
Application: 18/792,267 →
Publication: US US20250029877A1
THROUGH-DIELECTRIC-VIAS (TDVs) FOR 3D INTEGRATED CIRCUITS IN SILICON
Application: 18/828,400 →
Publication: US US20240429100A1
3D-Interconnect
Application: 15/493,917 →
Publication: US US20180308813A1
3D-Interconnect
Application: 16/245,925 →
Publication: US US20190148324A1
3d-Interconnect
Application: 17/340,469 →
Publication: US US20210366857A1
Embedded Organic Interposers for High Bandwidth
Application: 15/499,557 →
Publication: US US20180315735A1
Embedded Organic Interposer for High Bandwidth
Application: 16/555,127 →
Publication: US US20190385978A1
Techniques for Manufacturing Split-Cell 3D-Nand Memory Devices
Application: 17/362,557 →
Publication: US US20220005827A1
Region Shielding Within a Package of a Microelectronic Device
Application: 17/509,887 →
Publication: US US20220139846A1
Method of Forming a Region Shielding Within a Package of a Microelectronic Device
Application: 18/673,099 →
Publication: US US20240312928A1
3D-Interconnect with Electromagnetic Interference ("EMI") Shield and/or Antenna
Application: 17/525,559 →
Publication: US US20230154862A1
3D-Interconnect with Electromagnetic Interference ("Emi") Shield and/or Antenna
Application: 18/747,182 →
Publication: US US20240339418A1
Related Assignments (22)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Aug 6, 2015
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG
To: INVENSAS CORPORATION
Reel/Frame 036273/0332 →
Assignment of Assignor's Interest Feb 16, 2016
From: PRABHU, ASHOK S.; AWUJOOLA, ABIOLA; ZOHNI, WAEL; SUBIDO, WILLMAR
To: INVENSAS CORPORATION
Reel/Frame 037745/0863 →
Assignment of Assignor's Interest Feb 22, 2016
From: DELACRUZ, JAVIER A.; AWUJOOLA, ABIOLA; PRABHU, ASHOK S.; LATTIN, CHRISTOPHER W.
To: INVENSAS CORPORATION
Reel/Frame 037788/0660 →
Assignment of Assignor's Interest Feb 29, 2016
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 037856/0243 →
Assignment of Assignor's Interest May 5, 2016
From: WANG, LIANG; LEE, BONGSUB; HABA, BELGACEM; LEE, SANGIL
To: INVENSAS CORPORATION
Reel/Frame 038482/0396 →
Assignment of Assignor's Interest Jun 28, 2016
From: HUANG, SHAOWU; DELACRUZ, JAVIER A.; HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 039029/0312 →
Assignment of Assignor's Interest Oct 13, 2016
From: HABA, BELGACEM; CRISP, RICHARD DEWITT; ZOHNI, WAEL
To: INVENSAS CORPORATION
Reel/Frame 040007/0193 →
Assignment of Assignor's Interest Nov 17, 2016
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 040356/0191 →
Security Interest Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
Assignment of Assignor's Interest May 2, 2017
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG
To: INVENSAS CORPORATION
Reel/Frame 042214/0977 →
Assignment of Assignor's Interest Dec 7, 2017
From: SHEN, HONG; WANG, LIANG; GAO, GUILIAN
To: INVENSAS CORPORATION
Reel/Frame 044330/0420 →
Assignment of Assignor's Interest Dec 18, 2017
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 044422/0905 →
Assignment of Assignor's Interest Apr 23, 2018
From: DELACRUZ, JAVIER A.; AWUJOOLA, ABIOLA; PRABHU, ASHOK S.; LATTIN, CHRISTOPHER S.
To: INVENSAS CORPORATION
Reel/Frame 045610/0118 →
Assignment of Assignor's Interest Sep 20, 2018
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 046925/0650 →
Assignment of Assignor's Interest Nov 20, 2018
From: WANG, LIANG; KATKAR, RAJESH; SHEN, HONG
To: INVENSAS CORPORATION
Reel/Frame 047553/0588 →
Assignment of Assignor's Interest Apr 9, 2019
From: WANG, LIANG; LEE, BONGSUB; HABA, BELGACEM; LEE, SANGIL
To: INVENSAS CORPORATION
Reel/Frame 048831/0744 →
Assignment of Assignor's Interest Mar 19, 2020
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 052160/0754 →
Security Interest Jun 1, 2020
From: ROVI SOLUTIONS CORPORATION; ROVI TECHNOLOGIES CORPORATION; ROVI GUIDES, INC.; TIVO SOLUTIONS INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 053468/0001 →
Release of Security Interest Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION
Reel/Frame 052920/0001 →
Certificate of Conversion & Change of Name Apr 4, 2022
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 059581/0435 →
Change of Name Jun 14, 2023
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 063992/0106 →
Assignment of Assignor's Interest Jun 14, 2023
From: HABA, BELGACEM
To: INVENSAS CORPORATION
Reel/Frame 063949/0112 →