Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces

1. A vertically integrated microelectronic package, comprising:

a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the upper surface of the circuit platform having a wire bond-only surface area;

a first microelectronic device coupled to the upper surface of the circuit platform in the wire bond-only surface area;

first wire bond wires coupled to and extending away from an upper surface of the first microelectronic device;

a second microelectronic device in a face-down orientation coupled to upper ends of the first wire bond wires in a surface mount-only area, the second microelectronic device located above and at least partially overlapping the first microelectronic device;

second wire bond wires coupled to the upper surface of the circuit platform in the wire bond-only surface area and coupled to the upper surface of the first microelectronic device;

a protective layer disposed over the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the lower surface of the protective layer being in contact with the upper surface of the circuit platform, the upper surface of the protective layer having the surface mount-only area; and

the upper surface of the protective layer having the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.

2. The vertically integrated microelectronic package according to claim 1 , further comprising third wire bond wires coupled to and extending away from the upper surface of the circuit platform in the wire bond-only surface area with upper ends of the third wire bond wires coupled to the second microelectronic device in the face-down orientation in the surface mount-only area.

3. The vertically integrated microelectronic package according to claim 2 , wherein the protective layer is disposed for surrounding at least portions of lengths of the first wire bond wires and the third wire bond wires and for covering the second wire bond wires.

4. The vertically integrated microelectronic package according to claim 2 , wherein at least a portion of the surface mount-only area corresponds to the wire bond-only surface area.

5. The vertically integrated microelectronic package according to claim 2 , further comprising:

a third microelectronic device coupled to the upper surface of the circuit platform in a face-up orientation in the wire bond-only surface area neighboring the first microelectronic device with a gap therebetween; and

lower ends of the third wire bond wires and the second wire bond wires coupled between the first microelectronic device and the third microelectronic device to the upper surface of the circuit platform.

6. The vertically integrated microelectronic package according to claim 5 , further comprising:

a fourth microelectronic device in the face-up orientation coupled to the upper surface of the circuit platform in the wire bond-only surface area; and

fourth wire bond wires interconnecting the upper surface of the first microelectronic device with the upper surface of the fourth microelectronic device.

7. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device is a passive microelectronic device.

8. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device includes a capacitor of 0.1 or more microfarads.

9. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device includes a capacitor coupled to the first microelectronic device for a frequency response of 1 or more GHz.

10. The vertically integrated microelectronic package according to claim 1 , wherein the second microelectronic device is an active microelectronic device.

11. The vertically integrated microelectronic package according to claim 1 , wherein each of the second wire bond wires have approximately a nanohenry or less of self-inductance.

12. An inverted vertically integrated microelectronic package, comprising:

a circuit platform having an upper surface and a lower surface opposite the upper surface thereof, the lower surface of the circuit platform having a wire bond-only surface area;

a first microelectronic device coupled to the lower surface of the circuit platform in the wire bond-only surface area;

first wire bond wires coupled to and extending away from a lower surface of the first microelectronic device;

a second microelectronic device in a face-up orientation coupled to lower ends of the first wire bond wires in a surface mount-only area, the second microelectronic device located below and at least partially underlapping the first microelectronic device;

second wire bond wires coupled to and extending away from the lower surface of the circuit platform in the wire bond-only surface area and coupled to the lower surface of the first microelectronic device;

a protective layer disposed under the circuit platform and the first microelectronic device, the protective layer having a lower surface and an upper surface opposite the lower surface thereof with the upper surface of the protective layer being in contact with the lower surface of the circuit platform, the lower surface of the protective layer having the surface mount-only area; and

the lower surface of the protective layer having the second microelectronic device disposed thereon in the face-up orientation in the surface mount-only area for coupling to the lower ends of the first wire bond wires.

13. The inverted vertically integrated microelectronic package according to claim 12 , further comprising third wire bond wires coupled to and extending away from the lower surface of the circuit platform in the wire bond-only surface area with lower ends of the third wire bond wires coupled to the second microelectronic device in the face-up orientation in the surface mount-only area.

14. The inverted vertically integrated microelectronic package according to claim 13 , wherein the protective layer is disposed for surrounding at least portions of lengths of the first wire bond wires and the third wire bond wires and for covering the second wire bond wires.

15. The inverted vertically integrated microelectronic package according to claim 13 , wherein:

the protective layer is disposed to cover the lower surface of the first microelectronic device;

the upper surface of the protective layer being in contact with the lower surface of the circuit platform; and

interconnects coupled to the lower ends of the first wire bond wires and the third wire bond wires on the lower surface of the protective layer in the surface mount-only area.

16. The inverted vertically integrated microelectronic package according to claim 13 , further comprising:

a third microelectronic device coupled to the lower surface of the circuit platform in a face-down orientation in the wire bond-only surface area neighboring the first microelectronic device with a gap therebetween; and

upper ends of the third wire bond wires and the second wire bond wires coupled between the first microelectronic device and the third microelectronic device to the lower surface of the circuit platform.

17. The inverted vertically integrated microelectronic package according to claim 16 , further comprising:

a fourth microelectronic device in the face-down orientation coupled to the lower surface of the circuit platform in the wire bond-only surface area; and

fourth wire bond wires interconnecting the lower surface of the first microelectronic device with the lower surface of the fourth microelectronic device.

18. The inverted vertically integrated microelectronic package according to claim 12 , wherein the second microelectronic device is a passive microelectronic device.

19. The inverted vertically integrated microelectronic package according to claim 12 , wherein the second microelectronic device includes a capacitor of 0.1 or more microfarads.

20. The inverted vertically integrated microelectronic package according to claim 12 , wherein the second microelectronic device includes a capacitor coupled to the first microelectronic device for a frequency response of 1 or more GHz.

21. The inverted vertically integrated microelectronic package according to claim 12 , wherein each of the second wire bond wires have approximately a nanohenry or less of self-inductance.

22. The inverted vertically integrated microelectronic package according to claim 12 , wherein the second microelectronic device is an active microelectronic device.