Correction die for wafer/die stack
Representative implementations of devices and techniques provide correction for a defective die in a wafer-to-wafer stack or a die stack. A correction die is coupled to a die of the stack with the defective die. The correction die electrically replaces the defective die. Optionally, a dummy die can be coupled to other die stacks of a wafer-to-wafer stack to adjust a height of the stacks.
1. A method, comprising:
coupling a plurality of wafers in a wafer-to-wafer stack via a bonding technique that includes direct insulator-to-insulator bonding and direct metal-to-metal bonding, wherein each wafer includes a plurality of dies;
aligning the wafers such that the plurality of dies of each wafer couple to form a plurality of die stacks, each die stack aligned along an axis generally transverse to a plane of at least one of the wafers;
coupling a substitute die to a die stack of the plurality of die stacks via the bonding technique, wherein:
the die stack comprises an interchangeable die; and
the substitute die communicates with one or more dies of the die stack using a through silicon via (TSV); and
singulating the wafer-to-wafer stack into separated die stacks after coupling the substitute die via the bonding technique.
2. The method of claim 1 , wherein:
the substitute die is part of an alternate wafer; and
coupling the substitute die to the die stack comprises coupling the alternative wafer to the plurality of wafers via the bonding technique such that the substitute die of the alternate wafer is aligned to and coupled to the die stack that includes the interchangeable die.
3. The method of claim 2 , wherein the alternative wafer is a correction wafer.
4. The method of claim 2 , further comprising preselecting a thickness of the alternate wafer to determine an overall height of the die stacks.
5. The method of claim 1 , wherein the substitute die comprises a functional duplicate or functional equivalent die to the interchangeable die of the die stack.
6. The method of claim 1 , wherein the interchangeable die comprises an extra die, defective die, dummy die, non-operating die, die configured for non-use, or die used only to electrically couple together two other dies in the die stack.
7. The method of claim 1 , further comprising electrically substituting the substitute die for the interchangeable die of the die stack, wherein the interchangeable die is a defective die.
8. The method of claim 1 , further comprising coupling a carrier layer to at least one of a wafer of the wafer-to-wafer stack, a dummy die, and the substitute die.
9. The method of claim 1 , further comprising coupling a die stack of the plurality of die stacks including the substitute die to a logic layer comprised of one or more control components.
10. The method of claim 1 , wherein each wafer includes at least two dies electrically separated from one another.
11. A method, comprising:
coupling a plurality of dies in a plurality of vertical three-dimensional (3D) die stacks via a bonding technique that includes direct insulator-to-insulator bonding and direct metal-to-metal bonding, such that a footprint of each die stack is equivalent to a footprint of a single die of the die stack; and
coupling a substitute die, via the bonding technique, to a die of each die stack that includes an interchangeable die.
12. The method of claim 11 , wherein:
the substitute die is part of an alternate wafer; and
coupling the substitute die to the die of each die stack that includes an interchangeable die comprises coupling the alternative wafer, via the bonding technique, to the die of each die stack that includes the interchangeable die.
13. The method of claim 12 , wherein the alternative wafer is a correction wafer.
14. The method of claim 11 , wherein:
the method further comprises electrically substituting the substitute die for the interchangeable die of the die stack; and
the substitute die performs the entire electronic function of the interchangeable die.
15. The method of claim 11 , wherein the interchangeable die comprises an extra die, defective die, dummy die, non-operating die, die configured for non-use, or die used only to electrically couple together two other dies in the die stack.
16. The method of claim 11 , further comprising electrically coupling each die of a die stack to an adjacent die of the die stack using an interconnectivity layer having one or more electrical connections disposed within a perimeter of the adjacent dies.
17. The method of claim 11 , further comprising coupling a dummy die to a die of a die stack that does not include an interchangeable die.
18. The method of claim 17 , wherein the dummy die comprises an operational die, a non-operational die, filler material, or a portion of a reconstituted wafer.
19. The method of claim 11 , wherein the substitute die has a footprint that is smaller than the footprint of each die stack.
20. The method of claim 11 , further comprising coupling a die stack including a substitute die to a logic layer comprised of one or more control components.
21. The method of claim 11 , wherein the dies in the die stacks comprise singulated dies.