Embedded vialess bridges
View Patent ↗Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.
1. A vialess bridge, comprising:
a bridge substrate of a nonconductive material bearing electrical conductors, the bridge substrate capable of being embedded in a surface layer or a surface coating of a main substrate;
the electrical conductors comprising an array of signal, power, and ground wires; and
parallel vertical layers in the substrate, each parallel vertical layer made of individual electrical conduits, each layer of conduits interleaved with a layer of the nonconductive material to form a laminate block providing conductors for coupling a first die to a second die.
2. The vialess bridge of claim 1 , wherein the conductors for coupling a first die to a second die comprise horizontal conduits connecting first vertical conductors to second vertical conductors to enable surface-to-surface electrical connections on the main substrate using the array of the vialess bridge.
3. The vialess bridge of claim 1 , further comprising a working surface containing surface portions of the vertical conductors.
4. The vialess bridge of claim 3 , wherein signal, power, and ground connections are available at multiple locations and at regular intervals over the working surface.
5. The vialess bridge of claim 1 , wherein the bridge substrate is applicable to a surface of the main substrate to provide the dense array of signal, power, and ground wires for interconnecting multiple dies on the surface of the main substrate.
6. The vialess bridge of claim 2 , further comprising a working surface containing surface portions of the vertical conductors and wherein the horizontal conduits have a depth dimension relative to the working surface that is greater than a width dimension of the horizontal conduits relative to the working surface.
7. The vialess bridge of claim 2 , further comprising a working surface containing surface portions of the vertical conductors, wherein at least some of the vertical conductors extend from the working surface to another surface of the bridge substrate opposite the working surface.
8. An assembly, comprising:
a first substrate with conductive traces at a first line aspect;
a second substrate embedded in the first substrate with conductive traces at a second line aspect finer than the first line aspect, the second line aspect of the second substrate providing a denser array of conductive lines than the first substrate; and
parallel vertical layers in the second substrate, each parallel vertical layer made of individual electrical conduits, each layer of conduits interleaved with a layer of the nonconductive material to form a laminate block providing vialess vertical conductors.
9. The assembly of claim 8 , further comprising horizontal conduits between at least some of the vialess vertical conductors to enable point-to-point electrical connections on the first substrate of the circuit board using the denser array of the second substrate.
10. The assembly of claim 9 , wherein the dense array of the second substrate bridge provides a socket for a 3D-IC die or package.
11. The circuit board of claim 9 , wherein the dense array of the second substrate provides interconnects for a 3D-IC die or package.
12. The assembly of claim 9 , wherein the dense array of the second substrate provides interconnects between multiple 3D-IC dies or packages.
13. The assembly of claim 8 , further comprising a working surface on the second substrate homogenously covered with ends of the vialess vertical conductors.
14. The assembly of claim 13 , wherein the working surface provides signal, power, or ground connections at multiple locations and at regular intervals over the surface area of the working surface.
15. The assembly of claim 8 , wherein the second substrate is applicable to a surface of the first substrate of the circuit board to provide the dense array of signal, power, and ground wires for interconnecting multiple dies on the surface of the circuit board.
16. The assembly of claim 8 , further comprising multiple instances of the second substrate embedded in the first substrate, to provide multiple areas of the dense array of conductive lines on the surface of the circuit board.
17. The assembly of claim 9 , wherein the second substrate provides at least one signal conduction layer in one or more additional planes parallel to the plane of the surface, the at least one signal conduction layer comprising conductors at one or more vertical depths from the surface, a horizontal pitch of the conductors at the one or more vertical depths determined by thicknesses of the layers of nonconductive insulator material of the parallel vertical layers.
18. The assembly of claim 17 , wherein the at least one signal conduction layer comprises wide conduction traces or wires in at least one vertical plane of the parallel vertical layers providing a higher signal fidelity, a higher current-carrying capacity, a higher voltage capacity, or a higher power-carrying capacity than traces or wire routing on the surface of the first substrate of the circuit board.
19. The assembly of claim 8 , wherein the second substrate provides at least one power plane in a vertical plane or at least one ground plane in a vertical plane accessible to microelectronic devices on the surface of the circuit board.
20. The assembly of claim 8 , wherein the second substrate provides a vialess vertical conductor from a first surface of the assembly to an opposing surface of the second substrate.